Part Number: PCI2060
I need some more info. from TI for the PCI2060 (CWDS Internal Part number Reference- 17E653-10Z)
Power Dissipation ( Core & I/O)
Package thermal parameters
Reset timing specs, ( e.g. # cycles)
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Part Number: PCI2060
I need some more info. from TI for the PCI2060 (CWDS Internal Part number Reference- 17E653-10Z)
Power Dissipation ( Core & I/O)
Package thermal parameters
Reset timing specs, ( e.g. # cycles)
Hello Ivano,
Here are the device's thermal parameters.
Result- Theta JA-High K (standard datasheet value): 47.1
Result-Theta JC, top (standard datasheet value): 15.8
Result-Theta JB (standard datasheet value): 35.0
Result- Psi JT (standard datasheet value): 0.6
Result- Psi JB (standard datasheet value): 34.8
Regards,
Roberto
We would like to use :
66 MHz Primary Clock
33 MHz Secondary Clock
The application has all secondary bus clocks length matched including the 33MHz clock destined for the bridge.
Consequently, we do not need any of the secondary clocks generated by the PCI2060.
Ideally we would use the asynchronous secondary clock input ( 33 MHz) to clock the bridge.
Does S_CLK still need to be driven by a length matched 33MHz clock?
Can you confirm the configuration highlighted?