TMDS171: The output signal becomes unstable

Kenji Ohno1

Genius 5095 points

Part Number: TMDS171

Hi Team,

I would like to know the cause and measures of the problem.

The same phenomenon as the following situation has occurred in my customer.

https://e2e.ti.com/support/interface/digital_interface/f/130/t/620297

How did it solve it?

This case; Switching asynchronous signals with the same resolution will cause the output signal to become unstable.

Switching the input signal when using RETIMER mode (1080p60 → 1080p60)

The actual measurement is 1077 to 1080p60.

Best Regards,

Kenji

over 6 years ago

0 JMMN over 6 years ago

TI__Guru 60865 points

Hi Kenji,

Can you confirm the problem does not occur in redriver only mode?

Regards,
JMMN

0 Kenji Ohno1 over 6 years ago in reply to JMMN

Genius 5095 points

Hi JMMN,

Probably I think so.
In that case, how should I take measures?

Best Regards,
Kenji

0 JMMN over 6 years ago in reply to Kenji Ohno1

TI__Guru 60865 points

Hi Kenji,

If the customer has access to the I2C control lines of the device they can force the TMDS171 to redriver only mode using register 0x0Ah.

Regards,
JMMN

0 Kenji Ohno1 over 6 years ago in reply to JMMN

Genius 5095 points

Hi JMMN

Thank you for your answer.
I understood that it works in re-driver mode.
I would like to know why it does not work correctly in re-timer mode.

Best Regards,
Kenji

0 JMMN over 5 years ago in reply to Kenji Ohno1

TI__Guru 60865 points

Hi Kenji,

I wanted to confirm the TMDS171 works in redriver mode to rule out other possible issues. In retimer mode, there is a possibility of misalignment if one data stream starts before the others and the clock is already running. Enable sig_en on the device. Also if possible: delay hpd_snk going high when the source is connected or set applyrxtx after the clock is detected from the source.

Regards,
JMMN

0 Kenji Ohno1 over 5 years ago in reply to JMMN

Genius 5095 points

Hi JMMN,

Unfortunately my customers have already enabled sig_en.
Still a problem will arise.

I have some questions.
・Is it possible to avoid certainly by inputting signals in order of data stream → clock?
・How long should I delay between the data stream and the clock?
・Can TMDS 171 detect misalignment and clocks?

Best Regards,
Kenji

0 JMMN over 5 years ago in reply to Kenji Ohno1

TI__Guru 60865 points

Hi Kenji,

Inputting data before clock should address the issue. As long as all 3 data lanes have started before the clock, there does not need to be a specific delay. The TMDS171 can detect misalignment once the data lanes and clock are running, the only issue is the startup condition where some data lanes and the clock start early.

Regards,
JMMN

0 Kenji Ohno1 over 5 years ago in reply to JMMN

Genius 5095 points

Hi JMMM,

I would like to know below.

・Which register should I read to detect misalignment?
・Where should I check whether Clock is entered?

Regards,
Kenji

0 JMMN over 5 years ago in reply to Kenji Ohno1

TI__Guru 60865 points

Hi Kenji,

Please accept my friend request.

Regards,
JMMN

0 JMMN over 5 years ago in reply to JMMN

TI__Guru 60865 points

I am closing this ticket since we will resolve it over direct communication.

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TMDS171: The output signal becomes unstable