SN65DP159: DDC / I2C Conditioner?

It might be a routing issue can you please post a picture of the layout of the DDC lines?

See attachment....

SCL AND SDA REVIEW.pdf

My apologies, I must have missed the notification where you requested a schematic.  HDMI Circuits.pdfPlease see attachment.  The circuit connected to an HDMI connector is the one that works fine. 

Dongle reference design = page 43 of SN65DP159/SN75DP159 Datasheet (SLLSEJ2D –JULY 2015–REVISED JUNE 2017) 

Per the SBC's mfr spec, SBC_DDI3_CTRLDATA_AUX- and SBC_DDI3_CTRLCLK_AUX+ are DDI3 clock and data with 100kOhm pullups.  

Ok, I think the issue is that the FPGA that you are using does not support clock stretching. can you check if this is correct? You need to follow the note below if the FPGA is does not support clock stretching.

Actually, I'm not testing with an FPGA yet.  For testing, I have an adapter board that attaches to J8 but brings the signals to a standard HDMI connector.  I use the same sink, whether I test DDI2 or DDI3.  (The monitor has two selectable inputs).  (Again, DDI3 works; DDI2 does not.)

But maybe you have a good point... perhaps DDI3 is on edge, but happens to work more consistently (if that's even possible).  So maybe DDI2 needs the I2C conditioner, but bypass SCL_SRC and SDA_SRC like you said.  I will give this some thought...

Thanks.  Let me know if you can see any other issues.  

- Hong

Not yet... I need to figure out how to read those registers.  

I think you're talking about bytes 0x50 to 0x56 in the EDID string?  I have an EDID dump from the monitor, which I can obtain... but need time, as I need to put together a 3rd test unit (as the first units have moved on to other tests).... will follow up when I get the next unit assembled....   

My test equipment and unit is currently in the lab and is inaccessible for a while.  Perhaps I can ask, what should I be seeing on registers 0x50 to 0x56?