I need to interface the Amulet Technologies' GEMexpress II Display Driver Board with the TIANMA 10.4 inch 800 x 600 ransmissive LED Backlight TFT Touch Panel LCD Display (TM104SBH01).
The Tianma display has an 18-bit LVDS interface while the Amulet board has a 32-bit RGB interface.
Is it possible to interface these two boards with the DS90C365A ?
Thank you beforehand for your help. Best regards
Greetings -
Most likely more information is needed about the 32-bit RGB interface, that sees a bit odd to me, usually it is 18-bit (6bpp) and 3 control for 21 inputs of 3.3V LVCMOS. This is applied to the DS90C365 and converted to a 3D+C LVDS interface which sounds like what you called 18-bit LVDS (6bpp).
Your 32 bit might be 10bpp for 30 bits and VS and HS, in that case take the control signals and the MSBs (6 each of each color) and map to the part. Please review the datasheet and also watch clock polarity on the input.
Best Regards;
John Goldie
DPS APPS
John
You are absolutely right; the interface is 24-bit, not 32; this was my mistake while writing the question.
The GEMexpress II from amulet has 8bpp per color for a total of 24-bit. It is structured as 8-bit R, 8-bit G, and 8-bit B.
From what I understand, I can map the 6 MSBs of RGB (6 per color) from the GEMexpress and all other control signals (HSYNC, VSYNC, and DE).
If this is the case, it seems straight forward.
However, I still have a question, what type of CLK should I feed to the FPSHIFT?
Should I feed 1 clk period after the end of each frame? In this case, it would be after the 480000 pixel's information have been transferred to the display; is this correct? This would be the LVDS clock on the output side.
Or, does this FPSHIFT pin requires some specific timing required by the display?
Thank you beforehand for your help.
Greeting -
You are correct you have 8bpp source and a 6bpp display, therefore simply map the 6 MSBs per color to the part. Check the specs on the display datasheet to place the color in the correct order. You also need to transmit VSYNC and HSYNC and DATA ENABLE control signals across the LVDS interface. FPSHIFT is another name for PIXEL CLOCK (PCLK) it is a running clock typically about 65MHz for a XGA resolution display. Please see Fig 6 in the DS90C365A datasheet for clock edge relationship which is programmable with the R/FB pin. The cable between the SER and DES should be low skew to meet the DES RSKM requirements also.
Thank you for the clarification.
What type and/or brand of cable would you recommend? I seached the internet and there are many types of low skew cables.
Will a flat ribbon shielded cable do the work? Or, is a twisted pair type of cable with shielding better for the transmission of the LVDS signals?
Thank you beforehand.
Best regards.
Hi -
The cable selections is application dependant. Rate, length, and environment all come into play. If this is a short embedded applications, flex, or flat is common. If this needs to run though a small hollow hinge, discrete twp have been used. How much skew you can tolerate is again a balance of the media and what the DES device can accommodate. I assume you have a short link, If you are proto-ing it, I would start with flat cable and use a G S S G assignment of the connectors (G = Ground and S = Signal - this keeps the pairs together and isolated between each others). Also flat cable is very low skew also (all in parallel).
Best wishes with your application!
Thank you John.
I will start the prototype.