This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

PCA9518 runt clock

Other Parts Discussed in Thread: PCA9518

 I have a PCA9518 in a 3.3V system with 1.24K pull-up resistors. I'm seeing runt clocks on the SCL0 port as though the PCA9518 is incorrectly back-driving the clock from the SCL0 port.  The behavior stops if I add 100 Ohm resistors between the microprocessor and the PCA9518 SCL0 and SDA0 ports.  Not every clock cycle experiences the runt but, when it occurs, the I2C transaction is disrupted.  This is especially a problem with writes to any I2C device, in my case I have EEPROM on the I2C bus.

  • It is unfortunate that this is causing problems in your system, but this is exactly the behavior described in page 10 of the datasheet, which is also shown in Figure 4 on page 11 of the datasheet.

    "When one port of the PCA9518 is pulled low by a device on the I2C bus, a CMOS hysteresis-type input detects the falling edge and drives the EXPxxx1 line low; when the EXPxxx1 voltage is less than 0.5-V VCC, the other ports are pulled down to the VOL of the PCA9518, which is typically 0.5 V."

    This is called a "static offset" and it is deliberate in the design as a means of direction control.

    The 0.5 V static offset is surely not higher than the VIH level of any connected devices, so can you explain exactly how it is negatively affecting your design?

  • Looking at the scope shot you have (zoomed in all the way), I see that the voltage on your I2C line increases to ~1V since the scope is set to 2 V/div.

    This behavior is similar to the issue described in the errata, which is most obvious when CLK stretching is used.

    The simple way to solve this is to increase the resistance (reduce the "strength") of the pull-up resistors.