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PCA9306 Level translator problem

Other Parts Discussed in Thread: PCA9306

HI,


I used this IC to convert from 3.3V rail to 1.8V rail and vice versa. And I used 1.5k resistor as pullups on the both sides. On the SCL and SCL lines at the 1.8V side, Iam getting 2.3V. this voltage persists even after the pullups are removed. Also I confirmed that the destination side is not at all loading. The voltage is actually PCA9306 is sending out even the pass transistors are in off state.

Kindly can someone help me with the appropriate solution.

  • Hi Arun,

    I am moving this post to the I2C forum for more support. Can you provide a schematic of your system to help us better diagnose the issue?

    -Ryan

  • Hi Ryan,

    Even I replaced the R47 with 200k value. Still I am getting the voltage across 1.8V side I2C lines as 2.27V. I confirmed that the load side in not consuming current by pulling the enable pin low. At this condition all the IOs are at the high impedance state, hence same 1.8V is retained at the output side.

    why i am getting 2.27V ? please help me out

  • Image is not inserted in the above mail.

  • Can you show a scope shot of SCL1, SDA1, VREF1, and VREF2 with labels and the best y-axis resolution possible (500mV per division or better)? Please use the appropriate time scale as I cannot predict what time scale will be appropriate, and try to capture this during start-up and during I2C communication.

    I know this may be a dumb question, and we definitely need to get to the root of the issue, but:

    Does it really have an impact on the system if SDA1 and SCL1 = 2.27 V while high? As long as VIL and VIH are met, then will a slightly higher voltage cause damage to anything?

  • Hi,

    Thanks. I understand the problem. Here in the schematics attached, I forget to limit the current for other channel and hence its swinging is from 2.9V to 0.3V

  • I never saw the attachment with the schematic for this question until now.

    R47 needs to be between VREF2 and VCC_3V3.

    This is the problem, because the schematic does not match the datasheet's "Typical Application Circuit".
  • I, too, am seeing no level translation.

    Channel #1 is SDA 1V8 side & channel #2 is the 3V3 side (or possibly the other way round).  Either way I see no level translation.  The circuit is exactly as Fig 2 in the TI datasheet with 3k3 pullups on the 3V3 side & pullups removed on the 1V8 side.

    I've used I2C level translation chips before & even have design an FPGA block for this function.  I didn't get this.

    We do have power down intervals on the 1V8 side.  Could this be the problem?

  • Hello,

    Can you post your schematic?

    With the waveform you posted, I am very confident that you have VREF2 tied to the voltage rail directly. This is incorrect, please see the datasheet application section.

    Vref1 should be tied directly to the lower voltage supply and EN and Vref2 should be shorted together, and then pulled up to vcc2 (higher voltage rail) through a 200k resistor. Do not directly connect vref2 to the power rail.

    Best regards,

    Jonathan

  • As you can see we DO NOT have Vref2 directly connected to the 3V3 voltage rail.  I did lie about the exactness of our schematic compared to the datasheet - Vref1 is actually connected to 1V8 via a Schottky diode.  I believe this was implemented to cope with problems connected with the 1V8 powerdown.  Same applies to the 'NOT FITTED' pull up resistors R317, R318 I believe.

  • Hello,

    You definitely are correct with your EN and Vref2 connection. Normally the non-translation issue is a result of vref2 being tied to the rail.

    In this case, I would say that the issue is a result of your series diode on vref1 The enable pin voltage controls the translation. Since you are introducing a diode drop in the path of the voltage input, this is dropping the bias voltage most likely.

    I would suggest you remove the diode, add in the pull up resistors on SDAA/SCLA and I would suggest the following to handle vref1 powering off:

    Use a FET connected at the EN/VREF2 Node that pulls the node to ground when VREF1 Goes low. Using a gate driver or inverter to control the gate, you should be able to pull the EN node down and put the device in a high impedance state.
  • I put a 0R link in place of the diode, added 2k2 pullup resistors & wired the top end of R315 to the 3V3 logic line that enables the 1V8 supply.  

    This works!