We want to implement a circuit like in the picture below, were the VCC is connected to the lower voltage (SD0, SD1) instead of the SDA voltage, in this case 1.8V and we are not sure if the Vcc must be 1.8V or 3.3V, we have some concern that Vpass is too close to 1.8V, and in the other case connecting to 3.3V we have the concern that the voltage diference between Vcc and SD0 can have some how closed the fets, so can you help us clarify if the design connectivity is OK or there is any risk? Thank you in advance.