Hi, I have 19 singnals to be translated from 1.8V to 3.3V and another 19 signals from 3.3V to 1.8V 18 of them are data lines at 250Mbps and 1 is clock at 250 MHz. The data lines are synchronizes with the clock. Please suggest which voltage translator would be appropriate?
Regards, Ashish
Hi, Ashish,
250MBPS should be no problem for our part(SN74AVC20T245), but 250MHz maybe a challange, I will double check with more persons to find the perfect part which can support 250MHz tranlation. once I get it , I will provide the confirmation to you. suppose next week, I will let you know.
BRJunjie
Hi,
gentle reminder !
Regards,
Ashish
Sorry for late, our part SN74AVC1T45 and SN74AVC2T45 can work for 500MBPS(250MHz) when 1.8V to 3.3V translation. you can use it for the clock translation, and use SN74AVC20T245 for the Data translation(250MBPS).
But for 3.3V to 1.8V translation, we can not find the perfect part which can work at 250MBPS for 18 data lines. and also no part can be work well at 250MHz for clock translation for 3.3V to 1.8V translation.
you know the speed will be related to the capacitve load, what we talked is for the 15pF, the less load, the fast speed, if your load from 3.3 to 1.8 is less than this, maybe you could let us know the load, and we can do some simulation to check whether our part is Ok from 3.3V to 1.8V translation with that capacitive load.
BRjunjie
Data lines are synchronous with the clock. If I use different parts then skew will be introduced between data and clock as the propagation delays of SN74AVC1T45 and SN74AVC20T245 will be different. How do I solve this problem?
Yes, you are right. the two parts will have the much skew, and it is diffcult to implent the synchronization between clcok and Data.
But unfortunately, so far, we don't have the bus translator which can work up to 250MHZ. sorry for that.
Maybe one solution for you is to use the resistor to implement voltage split for the clock signal(like one 5V need, and three resistors, then get the 3.3V output) , and SN74AVC20T245 for data lines, and contorl the PCB trace of clock to make sure they have the same delay. for Tpd on SN74AVC20T245, you can use 2ns to calculate the delay on Dataline(from 1.8 to 3.3V, the Tpd range is 0.5 to 3.5ns), it is just my suggesition, not sure it can be implemented in your design. you need to calcuate your timing carefully to make sure the maring on Tsetup and Thold.
but from 3.3V to 1.8V translation, the SN74AVC20T245 can only support 210MBPS, and we don't have other parts can support 250MBPS. what I said is for 15pf load, if your load is less than this, maybe we can do the simulation on SN74AVC20T245 at that load, whether 250MPBS can be supportted. if yes, that will be great, and you can do the same voltage split on clock signal.
This is the only way I can get for your solution, just my suggestion, hope you can find some perfect parts to implement your design.
Any further thing, please let know.