Good Day All,
we investigate use of the CD40109B for level-shifting between 15V CMOS and 3.3V LVCMOS (low->high and high->low). A few questions:
Thanks & Regards,
We do not have any data at 3.3V. The propagation delays in this range would be very large.
I dont have any other solution for 3.3V to 15V.
We didn't find a 3.3V <--> 15V solution so we might have to go 3.3/5/15V if the CD40109B is not suitable.
Any information about power-down behaviour of the CD40109B?
You cannot have a voltage on the inputs or outputs if the power rails are at 0V unless you limit the current to less than 10ma. There clamp diodes to gnd and the rails.
What we have to understand is the high-Z state of the output side during power-down of the input side.
Some background on the application:
On side (A) is a FPGA with 3.3V LVCMOS with one supply system (3.3V & 5V). We can level-shift the FPGA to 5V CMOS.
On side (B) is a proprietary industrial bus using 15V CMOS logic with separate supply system.
When side (A) goes down we have to ensure that I/O on (B) are high-Z, so the bus is not disturbed
The notes on the first page of the datasheet under applications seems to indicate that if either side goes down it will be Isolated.
That is all I have to go by. SInce this is a part that was purchased from Harris I have no other data to look through.
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