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SN74ALVC164245DGGR bus hold

Digvijay Bhati1
Prodigy 10 points

I am using a SN74ALVC164245DGGR for level translating ( 3.3V-5V) data bus in my application.

1. The datasheet mention that “The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.”

Does this mean that a Pull-up or pull-down on data bus is essential if this level shifter is used ?

 2. Port A is connected to 3.3V microcontroller; Port B is connecting to 5V asynchronous memory.

Initially direction control signal (DIR) is set such that the data direction is form port B to A (memory to microcontroller). Oscilloscope digital probes are connected at port B, the probed data is 0xF0F0.

Now the direction control signal inverted and the direction is from A to B. no data is emitted from micro-controller which at Port B side.

Till the time some data is emitted from micro-controller the data 0xF0F0 remains latched on portB.

 

Does this level shifter have a bus hold circuitry implemented?

  • 0
    TI__Expert 6430 points

    Hi,

    For question1, the input state should be fixed (high or low ) when device is on normal operation to prevent since if input is floating the input circuit current (ICC, ICCZ) could be high. For example, Input signal is connectted to inverter. When input is at VDD/2, the current will be high.

    For question 2, if  changing data transfer direction,  the output could be hold last time state since the input is floating. Please put the fixed state at input when device is on noraml opertion.

    Thanks

    Wei