TXS0108E - oscillates when the signal rise/fall time is very slow

Hi Antony,

For TXS0108E, theinput transition rise rate or fall rate should be less than 10nS/V. If the value is more than 10nS/V , the abnormal behavior could be occurred.

Could customer add external pull-up resistor to accelerate the input rise edge? please try 1k pull up resistor.

For SN74LVCH8T245, the input transition rise rate or fall rate also need to be less 20nS/V,10nS/V or 5nS/V at different voltage. Thus, is is better to test SN74LVCH8T245 at slow input  like customer input.

Thanks

Wei

I just also had this issue. This is the curve I see on a rising edge:

Can someone from TI explain why this is happening? I got 3v3 on one side, 1v8 on other side:

All low volt side comes from a fast edge open drain FPGA IO (with no internal pullup), and the other side has a load of two devices, that are open drain (and can pull down). Routing is <40mm long trace. No ext pullups.

The falling slope just after the rising seems to pass Vil, wich may be interpreted as a falling edge going back the other direction, causing oscillations. As far as I understand, the middle Npass FET is causing this, but I dont know why. Adding ext pullup to high volt side stops it oscillate, but also dc-shifts the curve up. Adding a high 33k series resistor on high voltage side seems to clean up the pulse nicely, but it wont work in the other direction.

Can anyone at TI suggest what can cause this drop in level just after a rising edge? I seem to have low enough capacitance to charge to correct logic high, but something funny happens after the hard high pull. But the falling edges are perfect.

Thank you Wei for your prompt response.

Is there any danger in having the rise/fall time exceeding the maximum SN74LVCH8T245 specifications?

Q1 )  The signal rise/fall Is slow – in the 30-40 micro-seconds range but it’s monotonous, I wonder if except for some excess of current there will be any damages. Or long term misbehavior of the part.

Q2 ) Is there a quick formula to calculate the raise and fall time?

Thanks

Antony C.

Hi Antony,

It is hard to estimate the rise and fall time since the value will depend on input driver, trace load and input pin capacitance. In general,  use I=C du/dt to estimate the rise or fall edge. I means input current, C means capacitance load.

Thanks

Wei

Hi

Could you zoom in rise edge and provide oscillation signal PCB trace? if PCB trace is too long, the reflection signal will casue device unnormar behavior.

Thanks

Wei

Thansk Wei,

I am going to ask for those shots. by the way do you know if we have any voltage translator part that can support 30-40 micro-seconds rise/fall signals 

Thanks and regards,

Antony C.

Wei,

The customer just add that the conditions of the input from the power supply is more like a one-time status signal, i.e. it changes once in a while to indicate a PS failure. In theory if everything is good, this signal goes from low to high at power up and stays there until next power cycling. They dont mind having a pulse as long as there are no endless oscillations that occur on the TXS0108E device.

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What are your thoughs on the behavior of SN74LVCH8T245 under those conditions?

Thanks Wei for your support!

Antony C.

First, Antony, my apologies if Im causing noise on this thread. I was kinda hoping we could learn from our common problem, although we may have different problems. I do see there are other theads on this subject too, and most seem to just give up the txs010x.

Wei,

Here is MY (not Antony's) zoomed rising edge (I can do max 2GSa/s with my scope). The impedance on the track should be ~50ohm (with a tiny stub), but I assumed at <40mm long any reflections should happen within the 10-30ns duration of the hard pull. Below is also a screen capture of my routing. Note that I did not make a lot of effort to close the probe loop, so there is probably slight probenoise present in the images.

Can you tell us anything about symptoms of too high capacitance, or excess reflections? How about over/undershoot presence? With a critical device like that, common pitfalls should be better documented.

Our manufacturer bought a reel of 2k of these devices so I was hoping to stick with it rather than moving to the SN74GTL2003, but Im loosing my hopes.

The highlighted track is the high voltage side of the probed signal (probed at txs0108e pin). The blue is rear pcb side (layer 10) with the txs0108e, and red is top side with two 3v3 devices. Purple is layer 9. Both layer 8 and 10 has fillings that are not shown here, wich do add capacitance. The dimension is in mm. I did not show the low voltage tracks, as they are simple point to point ones, but slightly longer (~60-70mm), also 50ohm impedance.

Hi guys,

I am migrating my quesiton to a new post to avoid confusions

please, find link below thanks

http://e2e.ti.com/support/interface/etc_interface/f/391/t/338481.aspx

Antony C.

Hi Morten,

From waveform, it seems that there is re-settle progress when internal one-shot circuti finished the rise edge acceleration. In addition, adding pullup resistor on high side can fix the issue(just from A to B) and introduce DC offset. It seems that there is resistor between the ground on the signal.

Could you please gvie the test pull-up resistor value and test resistor between output and ground. Could you just test input driver device+TXS0108E? 

I think that removing the backend device can help to debug the issue.

Thanks

Wei