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LSF0108 Level Shifter TTL

Mohamed Hellal
Intellectual 2285 points
Other Parts Discussed in Thread: LSF0108

Hello, 

I have one question with the LSF0108 level shifter..

Here is the use case: FPGA/Periph <--> LSF0108 <--> uProcessor

The µP can drive only up to 2mA max at low level, I cannot use a low value of R for pullup on the B port of LSF0108.

The processor has a TTL level for inputs, and from DS the LSF0108  turns off the FET at 3.3V -0.5V =2.8V (Vref_A - 0.5V)

  • It Means I have at TTL level  2V up to 2.7V driven by FPGA CMOS driver( Pushpull) and after 2.8V is pulled  by the R pullup on B Port ?
  • The range 0 to 2.7V is driven by CMOS and I have a fast time, and does it mean when the level is higher than 2.7V, the FET turns off and the  port B is driven by the pullup ?

If the signals Rise time is 1ns at input of port A in range 0 to 2.7V,  and the delay of LSF 1.5ns,

Is the output signal at port B transmitted and driven by CMOS FPGA, before the FET is off ?

If Yes, is it ok to use some Pullup of 4.7K ?

Thanks,

Mohamed 

  • 0
    TI__Genius 9860 points
    Hi Mohamed, I am having some trouble understanding your question - it looks like you have multiple questions.

    What is the speed of your signal? This is the biggest factor in determining maximum pullup size.
  • 0 in reply to C. Ryan Land
    TI__Intellectual 2285 points

    Hi, Ryan,

    The signal speed is 8Mbit max (for one signal of the bus). Are the pull up required then in my configuration ? what shall be their minimum value ?


    Thanks,
    Mohamed

  • 0 in reply to Mohamed Hellal
    TI__Genius 9860 points
    Hi Mohamed, I apologize for the late response. I have had many requests lately.

    The pullup value for 8Mbit depends on the lengths of your traces. It is difficult to tell exactly what size pullup to use, but the pullup should be small enough so that the rise time RC constant does not affect the signal integrity. I recommend having several different values of pullup resistors available to test the system.

    Regarding the 2-V to 2.7-V FPGA, the FET will be partially turned off at 2.7 V and so the FPGA will only be partially driving the line to the uP. This is a very tough case to make a certain statement because you are so close to Vref_A-0.5. See the app note "Voltage Level Translation with the LSF Family", Figure 4. You can see the behavior of the output as the LSF device is "Partially turned off" at about ~0.6 V below Vref_A.

    But yes, you are correct about the fast rise time from the FPGA at voltages well below 2.7 V. from 0 V to 2.7 V, the FPGA will exclusively be driving the line to the uP, only starting to notice slight degradation in speed as you approach 2.7 V.