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SN74AVC8T245, 1 x SN74AVC4T245, and 1 x SN74AVC1T45 devices

sujeeva wettasinghe
Intellectual 460 points
Other Parts Discussed in Thread: SN74AVC4T245, SN74AVC1T45, SN74AVC8T245

I am seeing some quite strange things happen as we power down sections of the board.

 

To isolate the powered down sections, I have used a high-side switch, and then isolated all of the logic signals using 2 x SN74AVC8T245, 1 x SN74AVC4T245, and 1 x SN74AVC1T45 devices. The first three parts have been configured with their ‘A’ ports powered from the permanent supply, and their ‘B’ ports on the switched side. The final single gate part is configured the other way around (‘B’ port to permanent supply and ‘A’ port to switched side).

 

When I measure the current being drawn on the switched supply side, I see the system drawing around 36mA through the high-side switch, which represents a power draw of around  120mWatts, however, the system power draw increases by around 340mWatts.

 

There is nothing else in the system that I can identify that is drawing current, so I am left looking at the logic devices. Apart from two signals on the SN74AVC4T245 device, all of the signals on the permanently powered side of the logic gates are inputs, so any switching current I believe would be included in the current that I am measuring through the high-side switch. Also, there is only one signal that is switching, which is a 32.768MHz clock signal through the single gate part (again, input from the power side, with output on switched side).

 

Can you help me with a couple of questions, please?

 

  1. Are these devices suitable for use as digital isolators in partially powered systems? The datasheets seem to suggest that they are, but I thought I would check to make sure I haven’t completely missed the point.

  2. I have permanently connected the output enable lines for the SN74AVC8T245 and SN74AVC4T245 to ground. Could this be causing the devices to draw excessive current once their ‘B’ side power supply is applied? When I first designed the system, I did not notice the recommendation to keep the outputs disabled until both supplies are stable.
    There is a document that I read the shows the current drawn as the one of the two supplies is ramped up. This test did have the output enable signal tied low, so I would be surprised if this is an issue.

  3. While reviewing this, I have noticed that the datasheet for the SN74AVC1T45 suggests that the ‘A’ port supply should be applied first, and the ‘B’ port second. This is the opposite way from how I have the device at the moment. Is this likely to cause the part to draw excessive current? It doesn’t seem to be getting hot, and is operating normally.

I have been able to do some more investigation into the strange power issue.

The part that is easiest to remove is the SN74AVC1T45, and when I took this off the board and then linked across the data connection, I found that the current drop is pretty close to what I would expect it to be.

This means that I don’t believe this particular IC is drawing more current than it should.

The other parts are more difficult for me to remove, but I really can’t see how they could be the parts that are consuming the extra current.

Sujeeva Wettasinghe

Avnet FAE

 

  • 0
    TI__Guru* 96591 points

    Sujeeva,

    Can you post a schematic?

  • 0 in reply to Emrys Maier
    Intellectual 460 points

    5187.Schematic Prints.pdf

     

    The +3V3 rail is the main system power supply, and is always present. You will notice that there is a switch at the top of the schematic (U32) that controls the +3V3-A1 power rail. This switch is used to power down a section of the system to save power when it is not required.

     

    I have tested the system with U36 (the single gate part) removed. The drop in the power consumption was what I expected, so I not believe that the configuration of this part is causing the excessive power draw. Removing the other parts is more difficult with the equipment that I have at hand.

     

  • 0 in reply to sujeeva wettasinghe
    TI__Guru* 96591 points
    Moved to translation forum for support.
  • 0 in reply to sujeeva wettasinghe
    TI__Intellectual 2530 points

    Hi

    Everything seems ok with the configuration. Thanks for eliminating the power up sequence that may have been a concern with the U36.

    My key recommendation is to make sure that unused I/O ar not floating. For instance, in U35 - A2, B7, B8  needs to be at a defined state if these are unused. You can tie it to GND.

    Thanks

     

     

  • 0 in reply to Jennifer Joseph
    Intellectual 460 points
    As for the comment regarding the unused I/O ... A2 should be connected to the A1-RESETn net, but the connection got missed when I copied and pasted the schematics to send to you. B7 and B8 are outputs, as the direction control pin on U35 is permanently configured so that data is transferred from the A port to the B port. The input pins have pull-down resistors (A7 and A8).

    Late yesterday, I did find something else that I which I am going to look at today, but perhaps TI might be able to make a comment on as well.

    The signals A1-PWDN and A1-TESTn (U35 pins 7 and 8) are driven from a 2.5V power domain on the i.MX6 processor. Normally, I would not expect there to be an issue driving the input to a logic gate from a low voltage power domain (apart from the reduced noise margin), but I am wondering if there is something in the input structure of the SN74AVC8T245 device that might include pull-ups to +3V3. This could mean that the excess power is being drawn by the processor.

    I will look at the data sheet for the SN74AVC8T245 today, and if it is unclear, I might see if I can isolate these two pins on the logic chip to see if that makes a difference.



    have not found anything in the datasheet that suggests that this mode of operation is an issue, but in thinking about this, I had an issue some years ago with a logic device, which is not too different from what I am seeing now. In that case, it related to translating from one power domain to a different voltage power domain.

    Tomorrow, I will try to isolate the two pins and re-test to see if this explains the extra power drain.

    I know that the power is being drawn on the system power side of the buffers, rather than on the switched side, so we will see what I can find. Having excessive power being drawn by the processor itself, would be consistent with what I am measuring.

    The other thing I will look at is the power switch itself. I can’t imagine why this would be the cause of the problem, but it really is the only thing left to look at.
  • 0 in reply to sujeeva wettasinghe
    TI__Intellectual 2530 points

    Hi

    There are no internal pull-ups on this part.
    Please keep me updated on your debug and let me know if I can help with anything.

    Thanks

  • 0 in reply to Jennifer Joseph
    Intellectual 460 points
    I have just had a look at this, and I don’t believe this is the issue. In the current test mode, the signals are driven low, so this is not the source of the issue that I have observed.

    After doing some other testing with a resistive load, I am also quite confident that the power switch is not the where the additional current is being consumed.

    I am going to have a look at the only two signals that are outputs from the drivers on the system power side (in the schematics that I sent to you this is pins 6 and 7 of U34), as these are the only signals that I can think could have an effect on the system power side. All of the other pins are configured as inputs, and apart from the clock signal (which I have already tested), none of them are switching as part of my test.

    This is quite the mystery…
  • 0 in reply to Jennifer Joseph
    Intellectual 460 points
    I believe I have found the issue.

    It was slightly tricky to locate, but I have discovered that there are a couple of I/O lines on the i.MX6 that are not being initialised correctly by the bootloader. They do get set up once we open the various Linux devices, but this is causing a couple of the pins to be driving against the logic IC’s.

    I have just asked my software guy to look into this, but this is undoubtedly the problem.
  • 0 in reply to sujeeva wettasinghe
    TI__Intellectual 2530 points

    Glad to hear, thanks for the update.

  • 0 in reply to Jennifer Joseph
    Prodigy 20 points

    Hi Jennifer,

    I had a quick follow-up question regarding this bus transceiver; do you recommend using a series resistor for each input when pulling unused inputs to ground? I wanted to eliminate components, but concerned if there can be a moment during startup where there could be pins configured as outputs and sink excessive current. The DIR pin is tied to ground via a resistor and does not change. Thanks,

    Josh

  • 0 in reply to Joshua Wright87
    TI__Mastermind 23835 points
    Hello Josh,

    Sorry for the late response. Pulling the unused input directly to ground should not be a problem.