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TXB0102DCUR design issue

I am using this chip to do voltage level conversion between 3.3v and 5v on the UART TX and TX l;ines.

I have two  questions .

1)  The datasheet is saying the following:

" To ensure the high-impedance state of the outputs during power up or power down, the OE input pin must be tied to GND through a pulldown resistor and must not be enabled until VCCA and VCCB are fully ramped and stable"

I don't have an available GPIO to control OE .  can I use this chip in always "ebabled" and ready state  by pulling OE high ?

2) the datasheet is showing layout for multilayer boards  where the GND is placed on inner layers. I am only using double sided boards so what would be the layout for that ? 

also the by  pass capacitor is shown placed between the two pins .but the DCUR package pin distance is too narrow for any part placement between them.

I am showing the layout below please correct and advise.

  • Moving to the correct forum.
  • Hello Sami,
    1) Just tie a pull up resistor to OE to VCCA. This will keep the part enable at all times. You simply can't tri-state your outputs when you tie OE to VCCA.
    2) Before I give a recommendation can you tell me the data rates you are proposing to use? It will affect my recommendation.
    -FHoude
  • Here is how I might lay it out with only two layers.  I would try and keep signals on the top layer.  I would make sure my AC paths are short.  I put the pull up resistor on the bottom side, not sure if that is an option on your layout.  It is not as sensitive a node as your communications lines.  If you are going to go to high speed data rates then you will have to consider doing matched impedance lines for data signals.  Let me know if the layout isn't clear.  I have a picture of top (red) and bottom (blue) layouts.

  • hi !

    my datarates will be very low .. 9600 or 14.4K baud . 

    the picture is clear but i see two pics . i think one is posted by mistake ?

    should i lay a ground and power plane on top and bottom layers ? 

    and why place the R1 on bottom side ? i  am using double sided pcb so i can place it on bottom side.

    thanks

  • Hello Sami,

    The two pictures are of the top view but one has the top layer on top view and the other has the bottom layer on the top view.

    I placed R1 on the bottom because if you need to cross traces that would be the component that was least susceptible to noise.  

    I have attached another layout that doesn't involve components on the bottom, which should work fine.  I would suggest pouring a full ground plane on the bottom and try not to cut it up to much with traces and components. You can cut down on costs of the project if you only load parts on top.  It just makes for a more difficult layout. 

        

  • does it look good ?   i have attached the schematics and the board layout.

    regards

  • hi FHoude

    can you please approve this design so i can send the pcb for manufacturing?
    thanks
  • Why are there two grounds? GND and 5VGND??? Are the nets tied together somewhere?
  • hi

    i made the circuit exactly as you showed but just named the GND as 5vGND as  this will be the GND signal coming from the  5V system.

    if you see in the schematics the grounds are all connected together.

    regards

  • I just notices that the two nodes on the layout aren't connected together when they are close to each other.  That made me wonder how they were connected.  My opinion is to avoid using a lot of different ground ports in a schematic.  It can be confusing and it also can lead to errors in layout.  Otherwise, layout looks fine.

  • hi
    i would like to apply your suggestions to the schematic, can you point out what can i do to improve ?
    which two nodes arent connected ?
    regards