Hello,
I want to use SN74AVC4T245 with fixed DIR (DIR=H, A to B) and /OE=L for 1.8V to 3.3V level translation between a Hi-End FPGA with sensitive Outputs (@1.8V) and other IC's inputs (all supplied @3.3V). I cannot control the /OE or add pull-up resistors to input because of layout complexities.
According to SLVA746.pdf page 9/12: "Pull-up resistors are recommended on input ports (Rx is connected on Ax or Bx , whichever is the input), when the part is powered up in a permanently enabled state. This ensures proper/glitch free operation during power up. The value of the pull-up resistor needs to be such that the input follows its supply voltage VCC , as it ramps up. If the designer can ensure a high state at the input during power up, pull-up resistors are not needed."
What does proper/glitch free operation during power up mean above? Does this mean output impedance can be so low to draw a huge current form input/driver IF recommended pull-ups at input are not present? Or most probably just a data glitch at start-up?
In my application during power-on FPGA outputs are float @Hi-Z (or maybe & H or L) but I want to make sure there will NOT be any current draw (>1mA) from FPGA IO's during Power On/Down states because of /OE=GND during power-on.
Please let me know your thoughts?
PS: I was looking for something like x244 family (4 bit, small package no BGA) instead of x245 with fixed direction and no /OE but could NOT find any.
Thanks,
-Reza
