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DP83848 JTAG information

Other Parts Discussed in Thread: DP83848I, DP83848YB

I'm looking for the JTAG information on this PHY chip - although the data sheet calls out the interface, it does not actually provide any details as to the depth of the BSR or how long the instructions are.  Is there another document hidden somewhere inside the National website that I just can't find?  Thanks!

Mostly I need to figure out enough so that urJtag can bypass it properly.

 

  • The instruction length for the DP83848 devices is 5.  The BSDL file should include any additional information you might need.  The BSDL file for the DP83848 Industrial Temperature range is located at:

    http://www.national.com/assets/en/tools/ibis/dp83848i.bsdl

    The associated Logic Vision Software Boundary Scan Cell file is located at:

    http://www.national.com/assets/en/other/LVS_BSCAN_CELLS.txt

    If you are looking for information on another DP83848 variant, e.g. the DP83848YB, the main page containing the model files is located at:

    http://www.national.com/en/interface/ethernet/refdesign_demoboards.html

     

     

     

  • Wow - that was fast!  Thanks very much!

  • John,

    Can you help.

    I need a BDSL file for our ICT fixture,  went to site http://www.national.com/assets/en/tools/ibis/dp83848i.bsdl and cannot find it.

    It appears the National site has been broken up so not much available,

    Thanks

    Jay

  • Jay,

    Thanks for highlighting the outdated link.  I will get the BSDL file added to the DP83848I product folder.  I have attached the BSDL file and the associated Logic Vision Software Boundary Scan Cell file to this post so that you have them while we update the product folder.

    Patrick

    7444.3056.dp83848i.bsdl

    2158.4314.LVS_BSCAN_CELLS.txt
    package LVS_BSCAN_CELLS is
        use STD_1149_1_2001.all;
    	constant LV_BC_7: CELL_INFO;
    
    end LVS_BSCAN_CELLS;
    package body LVS_BSCAN_CELLS is
        use STD_1149_1_2001.all;
    	constant LV_BC_7: CELL_INFO := 
    	   ((BIDIR_IN, EXTEST,  PI),  (BIDIR_OUT, EXTEST,  PO),
               (BIDIR_IN, SAMPLE,  PI),  (BIDIR_OUT, SAMPLE,  PI),
               (BIDIR_IN, INTEST,  X),  (BIDIR_OUT, INTEST,  PI));
    
    end LVS_BSCAN_CELLS;
    

  • As a follow up, I moved this post to the Ethernet Forum.  This will make sure it gets the right visibility from the TI experts and will be visible to others on that forum who may be looking for the same information.

    Patrick