~20us Phase Error Offset

Bradley Higgin

I seem to be getting a ~20us discrepancy between my (t2-t1) vs (t4-t3) calculations, which I'm attributing to a ~20us phase offset in the master/slave ON_TIME marks.

t1: 1407275013.774174232
t2: 1407275013.774204842
t3: 1407275015.238881331
t4: 1407275015.238870992
t2-t1: 30610
t4-t3: -10339
Delay: 10135 ns
Offset: 0 sec
Phase: -204 ns

t1 is captured from the follow-up message
t2 is read from the RX timestamp register
t3 is read from the TX timestamp register
t4 is captured from the delayResp message

I must be missing a RX or TX timestamp compensation somewhere, but I'm not sure which one is wrong.

Tx,

Brad

over 9 years ago

0 Patrick OFarrell over 9 years ago

TI__Mastermind 31600 points

Brad,

I will look at this and see what I can suggest. Are these measurements in a single point to point system? In other words, the Master is connected directly to the Slave via a cable, without any switches or other hardware between?

Patrick

0 Bradley Higgin over 9 years ago in reply to Patrick OFarrell

Intellectual 525 points

Thanks, Patrick. At present, the master is connected to my slave via a switch.

0 Patrick OFarrell over 9 years ago in reply to Bradley Higgin

TI__Mastermind 31600 points

A standard switch or a PTP capable switch? If you connect the Master directly to the Slave, do you still see a similar offset?

Patrick

0 Bradley Higgin over 9 years ago in reply to Patrick OFarrell

Intellectual 525 points

Unfortunately, it's a standard switch. Connecting directly reduced this phase offset to ~800ns, and the delay discrepancy is ~800ns as well...

t1: 1407278527.925256424
t2: 1407278527.925257778
t3: 1407278528.847821931
t4: 1407278528.847821376
t2-t1: 1354
t4-t3: -555
Delay: 399 ns
Offset: 0 sec
Phase: -156 ns

0 Bradley Higgin over 9 years ago in reply to Bradley Higgin

Intellectual 525 points

My phase error calculation seems to off by ~200ns. I'm compensating for the sync event RX timestamp latency by adding 215ns (100Mb). Is there anything I'm missing?

Perhaps my algorithm is incorrect. Could you please confirm:

t_delay = ((t2 - t1) + (t4 - t3)) / 2;

t_offset = (t2 - t1) - t_delay;

Tx,

Brad

0 Bradley Higgin over 9 years ago in reply to Bradley Higgin

Intellectual 525 points

Bump

0 Patrick OFarrell over 9 years ago in reply to Bradley Higgin

TI__Mastermind 31600 points

Brad,

215ns is correct for the receive timestamp adjustment. Your t_delay and t_offset calculations look correct. Is your phase error a consistent 200ns? If so, over what period and what variation do you see?

Patrick

Interface

Interface forum

~20us Phase Error Offset