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Martin,
Could you share a schematic for review? In your testing, what is the link partner on the other end of the cable and what length of cable are you using?
Patrick
Hi Martin,
I just reviewed your schematic. Have you tried replacing the ferrite bead on the CT of the transformer with a 0 ohm resistor? Also, is there always a 3.3V supply connected to the CT of the transformer or do you disable this when you power down?
Regards,
Ross
Hi Martin,
What type of magnetics are you using? We recommend for this PHY that you use magnetics with choke. A typical one would be Pulse's HX1198FNL.
Regards,
Ross
Hi Martin,
Thank you for the updates. Is it possible for you to test with voltage still on the CT of the transformer (power down all other pins except CT of the transformer)?
Regards,
Ross
Hi Martin,
Sometimes it is advised to switch the CM choke to the device side and not the cable side. Would it be possible to wire your board with the choke on the device side?
Regards,
Ross
Martin,
Since the part is unpowered, I would expect any signaling on TD to be distorted and unbalanced. The common mode choke should effectively blunt this signal.
Patrick
Martin,
Yes, we recommend that the common mode choke be on the device side.
Patrick
Hi Martin, hi Ross,
Any news on this topic? We see the same behaviour on our target board (TLK110). I also see the behaviour on a TMDSICE3359.
Best regards,
Patrick
Hi Ross,
We now have tested a RJ45 jack with integrated magnetics which has a common mode choke on both sides (please see picture attached). The connected switch still establishes a link to the unpowered TLK110. Can you please tell us what the exact schematics of the magnetics should be?
Thanks and best regards,
Patrick
Hi Ross,
No there is no power to the TLK110 from an unexpected path. All the circuits are unpowered. Just the LAN cable is connected.
Yes, pin2 and pin 5 is tied to 3V3 rail. But not directly. There is a ferrit chip bead inductor in series (FBMH1608HM601) with 600Ohm @ 100MHz (please see picture attached, please note picture shows old RJ45 connector type).
If you can give me a direct contact I can share the whole schematic.
Attached are the signale that I have measured at the PHY (RD+, RD-, TD+ and TD-, please note the different scaling between receive and transmit signals).
Thanks for the support.
Best regards,
Patrick
Hi Patrick,
The link is because of the parasitic path that Patrick had pointed out in earlier posts.
It had been found that CMC between the device and magnetic reduces the risk of link in an unpowered state.
From what you have shown though is that the CMC is not helping to eliminate this issue.
You might need to try another RJ45 with CMC on the device side.
Kind regards,
Ross
Hi Ross,
Try another RJ45 is easier said than done. Finding one that fits with all the other parameters is difficult enought. Especially using integrated magnetics. As the same effect is on the AM335xICE V2 board I suspect that TI has no solution using a RJ45 with integrated magnetics that enables Auto-MDIX as well.
Is there no solution to modify the circuit around the PHY in some way?
Best regards,
Patrick
Martin, Ross,
What about having a Schottky diode from TD+ (anode) to 3.3V (cathode) and one from RD+ (anode) to 3.3V (cathode)? In the unpowered state this diode will short the pulse to the 3.3V rail. In powered state the diode will do nothing (except having a bit of a capacitance, around 6pF). I have tried this already with two BAT85 diode. It works with both the unpowered and the powered state. But I'm curious what the experts will say to this solution. Is there any downside?
@ Ross: Can you tell me how the pins TD+ and RD+ look like inside the TLK110? Do they have diodes to the supply rail? If so what kind of diodes?
Edit: I have now seen that with this modification I will only get a 10MBit/s connection to the switch.
Thanks and best regards,
Patrick
Hi Martin, hi Ross,
@ Martin: A Schottky diode from RD- (cathode) to GND (anode) and TD- (cathode) to GND (anode) does the trick. With this modification I cannot see a 10MBit/s link when the TLK110 is unpowered and I have the 100MBit/s link when I switch-on the board. Also 10MBit/s connection is still possible and Auto-MDIX is working fine.
My first attempt failed because I did not take into account that the signals at the PHY go beyond 3.3V rail (probably because of DC bias of center tap).
@ Ross: Is it possible that TI check this solution as well?
Best regards,
Patrick
Hi Ross,
It would help to hear the opinion of TI's TLK110/PHY experts to this solution. Maybe there are objections to this solution we have missed.
Thanks and best regards,
Patrick