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Block diagram DP83640

reto hermann
Intellectual 640 points
Other Parts Discussed in Thread: DP83640

Hi,

I'm trying to understand the PTP clock adjustment of the clock output and after reading the datasheet and the application notes I'm still a bit confused. Is there a detailed block diagram of the PTP clock section (FCO, PGM, clock divider, settings ot the PTP Clock Source Register and the PTP Clock Output Control Register ) 

Best regards

Reto

  • 0
    TI__Mastermind 31600 points

    Reto,

    The most detailed description of this device functionality is in the Software Development Guide (SDG).  The SDG is available in a zip file on the Tools & software tab (http://www.ti.com/product/DP83640/toolssoftware).  The direct link to the file is:

    http://www.ti.com/lit/zip/snlc036

    The zip file also includes a C Software Reference Library with examples of key functions.

    Patrick

  • 0 in reply to Patrick OFarrell
    Intellectual 640 points

    Hi Patrick,

    thank you for your reply.  I got a question regarding syntonization of two PHYs: In our hardware setup we have two DP83640 devices. The clk_out pins of the two devices are wired together and one is configured as output the other as input. The aim of that setup is to syntonize the two PTP clocks. My question concerns the PHY with the clock input:   When the CLK_SRC Bit of the   PTP Clock Source Register (PTP_CLKSRC) is set to 1x : (External reference clock) and we change PTP_RATE registers of that PHY, does this have an impact on the PTP clock frequency or not.? In other words: Is the frequency adjustment implemented before or after the CLK_SRC selection (PGM, divides PGM or external clock)

    Best regards

    Reto