DP83867IR: XGMII_ERR_INT Error in ISR register 0x0013

Hi Bill,

Can you send me a schematic of your design?

Does the ISR register clear after you read it and then stay cleared? RX_ERs can be seen on cable connect/disconnect but should not be incrementing during an active link. If you are experiencing RX_ERs, this usually indicates a problem with reference clock accuracy, jitter on the reference clock, or jitter from the transmitting link partner.

Best Regards,

Rob:

I messaged you the schematic. The RX seems to work fine. If I clear this register the XGMII_ERR_INT remains.

Thanks,

-Bill

Bill,

Thanks for the schematic. It says you have an 867E device, is this the 48QFN? If so, what is your link partner? A PC?

The DP83867E datasheet was updated recently, it applies to all 48QFN devices in the family. The RX_CTRL pin should be strapped in mode 3 or you can follow the suggested work around in the first note of Table 6.

www.ti.com/.../dp83867e.pdf

Best Regards,

Rob:

The part number is DP83867ERGZT. I've tried connecting to a mac, pc, and switch.

Can you attache the updated data sheet? I can see on the product page that the data sheet was updated last week, but when I click on the link the document that opens is marked rev * from 2015. I don't see any notes about a workaround in rev * data sheet.

Thanks,

-Bill

Bill,

I will privately send you the updated DS.  I think you have an issue with your web browser caching the old version.  

Best Regards,

Rob:

Thanks.  I received the data sheet.  I updated the RX_CTRL strap resistor to mode 3.  Unfortunately I still see the ISR Register 0x0013 showing a XGMII_ERR_INT (bit 2) that won't clear.  What could cause this error?

Thanks,

-Bill

Hi Bill,

If you are having a problem with XGMII errors, you are likely overflowing or under running the RGMII FIFO. Measure the accuracy of your 25MHz clock to the DP83867 and your MAC's reference clock. For the DP83867 use the CLK_OUT pin to measure the 25MHz clock so you don't disturb the crystal circuit with the scope probe. The DP83867's reference should be 25MHz +/-50ppm.

You can also increase the FIFO depth using register 0x32 which could reduce the FIFO overflow/underrun conditions. Change the TX FIFO threshold to 0b11 to increase the TX FIFO depth.

Regards,