I have a few questions on WoL interrupt generation on DP83867
1. There is little said in the datasheet about how destination address DA (regs 0x136-0x138 and pattern regs 0x13C..0x15B) interact. Do both DA AND pattern have to match to issue an IRQ?).
2. Pattern Match Data Registers has MAC address bits defined as [15..0], [31..16], [47..32]. I have the following MAC address 01:00:5E:00:01:81 and write those registers as 0x0001 -> 0x136, 0x005E -> 0x137, 0x8101 -> 0x138. Have I correctly understood the datasheet that lower byte needs to be written to lower byte of RXFPMDx and upper byte into the upper byte?
3. Description of RXFCFG (0x134):
Are bits WAKE_ON_BCAST and WAKE_ON_UCAST independent of WAKE_ON_PATTERN and WAKE_ON_MAGIC?
Can I use just two of them to cause an interrupt?
If I set WAKE_ON_BCAST is interrupt asserted on any broadcast packet or only one that matches pattern?
4. I set interrupts in the following way:
// enable enhanced receive features
write_phy_DP83867_reg(baseaddr_miim, phyid, MIIM_DP83867_CFG2, MIIM_DP83867_CFG2_INTPOL); // negate polarity
write_phy_DP83867_reg(baseaddr_miim, phyid, MIIM_DP83867_CFG3, MIIM_DP83867_CFG3_INT_OE); // enable driving INTZ line
write_phy_DP83867_reg(baseaddr_miim, phyid, MIIM_DP83867_RXFCFG,
MIIM_DP83867_RXFCFG_ENH| // enable WOL
MIIM_DP83867_RXFCFG_WAKE_PATTERN| // wake on pattern
MIIM_DP83867_RXFCFG_WAKE_UCAST| // unicast
MIIM_DP83867_RXFCFG_WAKE_BCAST| // broadcast
MIIM_DP83867_RXFCFG_WOL_STRETCH(3));
write_phy_DP83867_reg(baseaddr_miim, phyid, MIIM_DP83867_MICR, MIIM_DP83867_MICR_WOL); // Enable WOL interrupt
If I assert interrupts on purpose, i.e.:
write_phy_DP83867_reg(baseaddr_miim, phyid, MIIM_DP83867_CFG3, MIIM_DP83867_CFG3_INT_OE|MIIM_DP83867_CFG3_INT_ASSERT);
and
write_phy_DP83867_reg(baseaddr_miim, phyid, MIIM_DP83867_CFG3, MIIM_DP83867_CFG3_INT_OE);
I can see interrupt is asserted on INTN/PWDN line (pin 44), but not upon receiving a packet.
And the last one about RXFSTS (0x135) – when I read it I always read 0 from it. When I read back RXFCFG (0x134) I read exactly the bits I set up.
According to the datasheet (March, 2017) the following bits are defined:
UCAST_RCVD
BCAST_RCVD
PATTERN_RCVD
I see MAC receives packets and SFD line on GPIO pins show it but I never read back those bits from RXFSTS. Can I get WoL interrupt on non-matching broadcast packet?
Thanks!