• Resolved

DP83867E: DP83867E

Part Number: DP83867E

Hi, We are using the DP83867E in SGMII mode. To track a stability issue we would like to

enable loopback on the SGMII side of the PHY. That is : 

CPU -> SGMII-link -> DP83867E  -> SGMII-link -> CPU

Loopback mode is describe in 8.4.4 in the datasheet and Table 4 row 7

Digital.SGMII seems a good match. However I am a bit confused about 

which direction the loopback is operating and how to enable it. 

Can somebody tell me which register to set to enable the above SGMII 

loopback towards the CPU? 

Which mode should I select in BISCR.LOOPBACK_MODE (addr 0x16) ?

Additionally, do I also have to set other BISCR (addr 0x16) register flags?

Do I need to set loopback flag in BMCR(addr 0) 

// Greetings Konrad

  • Hi Konrad,

    The Digital loopback described in table 4 of the DP83867E datasheet is the "Digital loop" option in register 0x16 BISCR.LOOPBACK_MODE[5:2] bits.

    Set bit[5:2] to 0b0001 for digital loopback.

    Digital loopback is toward the MAC layer. MAC TX packets will enter the PHY, be looped back in the digital of the PHY, and sent back to the MAC layer.

    MAC ===> PHY SGMII ==> PHY digital ==
    .                                                                              ||
    MAC <=== PHY SGMII <== PHY digital <=

    With SGMII loopback you'll need to set the link speed on the cable in order to provide a status for the SGMII auto-negotiation.

    Best Regards,

    Rob Rodrigues

    EFL (Ethernet & FPD Link) Applications Engineer