Hi, We are using the DP83867E in SGMII mode. To track a stability issue we would like to
enable loopback on the SGMII side of the PHY. That is :
CPU -> SGMII-link -> DP83867E -> SGMII-link -> CPU
Loopback mode is describe in 8.4.4 in the datasheet and Table 4 row 7
Digital.SGMII seems a good match. However I am a bit confused about
which direction the loopback is operating and how to enable it.
Can somebody tell me which register to set to enable the above SGMII
loopback towards the CPU?
Which mode should I select in BISCR.LOOPBACK_MODE (addr 0x16) ?
Additionally, do I also have to set other BISCR (addr 0x16) register flags?
Do I need to set loopback flag in BMCR(addr 0)
// Greetings Konrad