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TLK105: RMII timing question

Part Number: TLK105

For an application connecting from PHY to MAC or PHY1 to PHY2 (back to back phy)

The RMII 50MHZ is coming from PHY1.

The set up and hold time at PHY2 is measured with respect to the 50MHz clock coming from PHY1.

If the length of the traces between PHY1 and 2 is 6 inches, then both Clock and TX signals are delayed by the same time. Basically no loss in timing budget.

But in case of PHY2 to PHY1, do you still measure setup/hold time with respect to the 50MHz clock of PHY1?

This would eat up significant timing margin.

2 Replies

  • Hi Hithesh,

    Yes, the TLK105l datasheet mentions that data is latched at the MAC with reference to the same clock edges as on the XI pin

    As per the RMII spec, a 50MHz reference clock is used for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and RX_ER. This can be sourced from the MAC or from an external source. T. The receiver in RMII communication (MAC or PHY1 in this case) shall account for differences between the local REF_CLK and the recovered clock through use of sufficient elasticity buffering.

    -Regards,
    Aniruddha
  • In reply to Aniruddha Khadye:

    Hi Aniruddha,

    Can you explain the last sentence please "The receiver in RMII communication (MAC or PHY1 in this case) shall account for differences between the local REF_CLK and the recovered clock through use of sufficient elasticity buffering"
    what is local REF_CLK and the recovered clock.
    There is no clock recovery in RMII?