Hello,
we are using DP83867E and we are seeing some issues with EEE and Flow control.
When EEE is enabled on a computer and then the computer is connected to our HW running DP83867E, we are able to get an ethernetlink (1Gbps/Full duplex) but no data arrive at neither end of the link.
Setup: Computer ===== DP83867E == CPU
We then found that a new datasheet sad been posted with a the strap values of RX_CTL had been changed and a note that said that bit 7 of register 0x31 should be cleared if RX_CTL HW strap if not set to 3 or 4. On our board RX_CTL is left floating so we implemented the register bit clearing instead and now we are able to transmit data between our HW and a laptop successfully.
We still wonder which type of errors the "clearing of bit 7 in reg 0x31" is fixing in DP83867E as we have seen other strange issues with truncated packages on both TX and RX link.
What type of errors would one see if the fix is not implemented?
BR
Andreas Hansen
Qamcom
