DP83867IR: Input data logic level

Mahesh KC03

Part Number: DP83867IR

Hi,

One of my customers is using the Xilinx SoC to interface with our phy. The 1.8V logic level from the SoC has a max value of 0.45V for the logic 0. In case of our device, the maximum level suggested in the datasheet for a 1.8V logic low is 0.2 x VDDIO(i.e. 0.2 x 1.8) = 0.36V

Would this 0.45V level cause an issue for the phy?

over 6 years ago

0 Rob Rodrigues over 6 years ago

TI__Mastermind 19780 points

Hi Mahesh,

No, this is not an issue for 2 reasons.

1. Our VIL threshold is higher than the 0.36 V published. We published this level to stay consistent with JEDEC standards. Our VIL can handle 0.45 V without concern.

2. The Xilinx spec is extremely wide because of the output current rating. Xilinx forums are heavy with questions about the Vol being very high. The response at Xilinx appears to be "use the IBIS model to determine actual VOL". See this thread, second comment: forums.xilinx.com/.../427880

Best Regards,

0 Mahesh KC03 over 6 years ago in reply to Rob Rodrigues

TI__Intellectual 1360 points

Thanks Rob.

Can you let me know what is the maximum limit for Vil?

0 Rob Rodrigues over 6 years ago in reply to Mahesh KC03

TI__Mastermind 19780 points

Hi Mahesh,

It is above 0.45 V. The rest is char data we can only release on a case-by-case basis.

Best Regards,

Interface

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DP83867IR: Input data logic level