Hi
I have question for XI clock timing.
According to the Figure 1 and 2 of datasheet, XI clock is input before VDD get stable.
However, XI clock (25MHz) can not be input before VDD is power up in the customer system.
Therefore, we are considering the following sequence. Could you please check if it is not problem?
1. RESET is being assereted while VDD is powered up. XI clock is absent.
2. VDD get stable, then XI clock is input.
3. RESET is released
BestRegards
