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DP83867E: Start up sequence

na na78
Guru 16770 points
Part Number: DP83867E

Hi

I have questions about start up sequence of DP83867E.

Q1.
According to the Figure 1 in datasheet, 32 MDC clock cycle is described.
Must the 32clock cycle be required after power-up?
Or is it just showing first read/write operation?

Q2.
In three supply mode, there is supply sequence that VDDA1P8 must be stable within 25ms after VDDA2P5 is ramped up but any other sequnece is not required. Is it possible to apply VDDA1P8(1.8V) and VDDA2P5(2.5V) when VDDIO and VDD1P0 is not powered?

Q3.
I could not get the meaning of NOTE described on Page 97 in the datasheet.
What is that note saying? VDDA1P8 can be ramped up before VDDA2P5? But I think it is inhibited by Talbe 107.

Q4.
There is no power sequence requirement in two-supply mode.
The NOTE mentioned in Q3 is not applied in two-supply mode. Is my understanding correct?

BestRegards

  • 0
    TI__Mastermind 23675 points
    Hi,

    Here are the answers to your questions:

    1. For the first MDIO/MDC transaction (either a read or write) you will need 32 MDC clock cycles. These clock cycles are not required after power-up. They are only there to indicate that if you want MDIO/MDC access you need the 32 MDC cycles for the PHY to respond or accept the write.

    2. There is no requirement on any of the other supplies besides the relation between VDDA1P8 (1.8V) and VDDA2P5 (2.5V).

    3. VDDA1P8 must not reach its final 1.8V stability point before the VDDA2P5 begins its ramp. VDDA2P5 ramp should lead VDDA1P8 ramp.

    4. No supply ramp requirement for two supply operation. This is correct.

    Kind regards,
    Ross