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DP83867CR: DP83867CR RGMII Timings/Constraints for Xilinx FPGA

Part Number: DP83867CR

Hello,

i'have a problem with RGMII timing constraint on Zynq with combination with DP83867 Phy

I learned, setting the correct input and output delay  is essential for a working device.

Could somebody tell me the right timing settings in vivado xdc? (undwer normal conditions, with optimal pcb routing)

I read the phy datasheet but I'm not shure which are the correct timings, and I don't know is the timing value set positive or negative.

In following there is an example, with non correct values.

Thank you very much

set phy_in [get_ports {phy_rxdv phy_rxd[*]}]
set_input_delay -clock phy_rxc -max -2.0 $phy_in  
set_input_delay -clock phy_rxc -max -2.0 $phy_in -clock_fall -add_delay
set_input_delay -clock phy_rxc -min 1.2 $phy_in
set_input_delay -clock phy_rxc -min 1.2 $phy_in -clock_fall -add_delay

set phy_out [get_ports {phy_txen phy_txd[*]}]
set_output_delay -clock [get_clocks phy_tx_clk] -max  2.0 $phy_out
set_output_delay -clock [get_clocks phy_tx_clk] -max  2.0 $phy_out -clock_fall -add_delay
set_output_delay -clock [get_clocks phy_tx_clk] -min -1.2 $phy_out
set_output_delay -clock [get_clocks phy_tx_clk] -min -1.2 $phy_out -clock_fall -add_delay

  • Hi,

    Can you send me a description of the Vivado options for internal delay?
    Also the range of delays supported?

    For the DP83867, we have an internal DLL on the transmit and receive path that are controllable in the register map.
    If you implement delay within Vivado, you can most likely operate the DP83867 in Align operation (i.e. no added delay applied to the RX_CLK or TX_CLK).

    Kind regards,
    Ross
  • In ideal case I want dont touch the skew registers in DO83867

    The timing constraint of Vivado is described here: www.xilinx.com/.../ug903-vivado-using-constraints.pdf from page 73 to 78
  • Hi Richard,

    If you are adding the receive and transmit delay in the vivado, please ensure that there is no delay added in the DP83867.
    How is your bootstrap configuration in the DP83867?

    Thank you,
    Ross
  • Hi,
    I just have the same question.
    I would like to get the XDC constraints for DP83867.
    The RGMII Timing section in the datasheet does not help as there are NOM and MIN values for Tsetup and Thold.

    Can you please provide the XDC constraints?
    Can you also please clarify the meaning of NOM and MIN values for Tsetup and Thold?

    Setup and hold times are limits. A violation against the limits results in malfunction which can’t be tolerated.
    So for me it makes no sense to have NOM and MIN values for Tsetup and Thold. As designer I can only implement either the MIN or the NOM value.

    Regards
    Bernhard
  • In my case, only botstrap RX_CTRL is pulled up with 2.49kOhm, all others are high impedance
    RX and TX clk are shifted with 90 degrees
  • Hi Bernhard,

    In the case of designing for the system, you should ensure the minimum setup and hold times are met.

    You will have to get XDC constraints file from Xilinx. We do not offer the XDC file.

    Regards,
  • Hi Richard,

    By default, the DP83867 delays the clock and data by 2.0ns on both the TX and RX side. If you want to enable the delays in your FPGA/MPSoC from Xilinx, you should strap the TX and RX clock skew to 0.5ns or 0ns.

    You could also disable skews by writing 0b00 to register 0x0032 bit[1:0]

    You are probably having issues because delay is being added by both the FPGA and the PHY, as Ross mentioned.

    Regards,
  • Hi Rob,

    thank you for your reply!

    Please have a look at the datasheet an tell me the setup and hold times for RGMII for DP83867.

    This information can't be provided by Xilinx but only by TI who is manufacturer of this component.

    Please tell me why are MIN and NOM values specified?

    Regards

    Bernhard

  • Hi Bernhard,

    This spec in the DP83867 datasheet matches the RGMII v2.0 spec as written by Broadcomm, Marvell, and HP. In that spec, a minimum setup and hold time is the only spec. You can derive the maximum from the idea that any part of the cycle not used by the minimum setup and hold time can be applied to one of the other timing parameters.

    Please look at this app note and hopefully it can clarify: www.ti.com/.../snla243.pdf

    In section 3 you can see we only consider the minimum setup and hold time to ensure reliable data communication.

    Maximum is of no concern as long as the next data cycle's timing is not violated.