Hello,
i'have a problem with RGMII timing constraint on Zynq with combination with DP83867 Phy
I learned, setting the correct input and output delay is essential for a working device.
Could somebody tell me the right timing settings in vivado xdc? (undwer normal conditions, with optimal pcb routing)
I read the phy datasheet but I'm not shure which are the correct timings, and I don't know is the timing value set positive or negative.
In following there is an example, with non correct values.
Thank you very much
set phy_in [get_ports {phy_rxdv phy_rxd[*]}]
set_input_delay -clock phy_rxc -max -2.0 $phy_in
set_input_delay -clock phy_rxc -max -2.0 $phy_in -clock_fall -add_delay
set_input_delay -clock phy_rxc -min 1.2 $phy_in
set_input_delay -clock phy_rxc -min 1.2 $phy_in -clock_fall -add_delay
set phy_out [get_ports {phy_txen phy_txd[*]}]
set_output_delay -clock [get_clocks phy_tx_clk] -max 2.0 $phy_out
set_output_delay -clock [get_clocks phy_tx_clk] -max 2.0 $phy_out -clock_fall -add_delay
set_output_delay -clock [get_clocks phy_tx_clk] -min -1.2 $phy_out
set_output_delay -clock [get_clocks phy_tx_clk] -min -1.2 $phy_out -clock_fall -add_delay