RTOS/DP83848C: Does DP83848C chip support Ethercat communication

As per the PHY selection guideline from Beckhoff (download.beckhoff.com/.../an_phy_selection_guidev2.5.pdf) the DP83848C chip is listed under "Example Ethernet PHYs assumed to fulfill EtherCAT requirements".

The sample Ethercat application under PRU-ICSS-EtherCAT_Slave_01.00.03.01 works with the Am335x Sitara IceV2 evaluation board (processor_sdk_rtos_am335x_3_03_00_04). The evaluation board uses TLK110 PHY chip. Now there are some configurations required for TLK110 PHY to make it work for Ethercat application (e.g. Force Full-Duplex, Disable detection of transmit error in odd-nibble boundary for odd nibble insertion, Led config to mode3, led blink rate, fast link down detection etc.)

In our custom board, we are using DP83848C PHY chip. What configurations are required for this PHY chip to work for Ethercat communication if I use it with same sample TI ethercat application? The above configurations of TLK110 are not applicable for DP83848 as most of the registers are different. So my question is can the DP83848C PHY chip be used for Ethercat communication with AM335x? If yes, then what are the configuration changes required?

The Beckhoff guideline says the enhaced link detection is required for Ethercat but does DP83848 support enhanced link detection? How can the sample TI ethercat application changed to enable enhanced link detection? Is enhanced link detection really required?

regards

Mohit