• State Resolved
  • Locked Locked
  • Replies 19 replies
  • Subscribers 35 subscribers
  • Views 6448 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Linux/DP83867IR: dp83867 output 125M clock

michael cao
Prodigy 230 points
Part Number: DP83867IR

Tool/software: Linux

Hi, we use TI DP83867IRRGZR PHY on Rockchip RK3288 platform. The 18 pin  CLK_OUT of DP83867IR need to provide 125MHz clock to meet CPU RK3288’s spec.

But it’s always 25MHz CLK-OUT. We had configured register[12:8](CLK_O_SEL) to 0x08,0x04,0x00, but the CLK-OUT is the same 25MHz,

and I back to read the register value, it’s my configured value.

So what can I do next?  thanks!

  • 0
    TI__Mastermind 23675 points
    Hi Michael,

    Why does the CPU need the CLK_OUT from the DP83867IR?
    Are you using RGMII? For RGMII, you need to just feed the MAC the RX_CLK.
    When the PHY is in 1G operation the clock will be 125MHz.

    Best regards,
    Ross
  • 0 in reply to Ross Pimentel
    Prodigy 230 points
    the rk3288 need another 125M clock from phy except tx/rx_clk,
    we using RGMII interface,and phy is in 1G operation,
    so we mast config phy to output 125M CLK_OUT to cpu.
  • 0 in reply to michael cao
    TI__Mastermind 18425 points
    Hello Michael,

    The DP83867 is able to switch between frequencies when controlled through register 0x170. Are there any other PHYs on the system with similar PHY address?

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 230 points

    we have only one phy。

  • 0 in reply to michael cao
    TI__Mastermind 18425 points

    Hi Micheal,

    The default value of bit [12:8] in register 0x170 is 0x0C which would output the 25MHz reference clock. When those bits are changed to 0x0B- 0x08 and 0x03-0x00, they will output 125MHz. Other bits of that register are dont care in this case and should be kept the same. I read 0x0C0E as default value on my setup and I keep the lower byte unchanged (0x0E) throughout the experiment.

    -Regards,

    Aniruddha 

  • 0 in reply to Aniruddha Khadye
    Prodigy 230 points
    I had configured bit [12:8] in register 0x170 to 0x08,0x04,0x00,the CLK-OUT is the same 25MHz,
    can you verify this problem in DP83867 demo board?
    thanks!
  • 0 in reply to michael cao
    TI__Mastermind 26320 points

    Hi,

    1. Can you read and share the register value of register 0x0170 after configuring [12:8] as 0x08.

    2. Which pin you are measuring the clock out ?

    3. Kindly share the schematics.

    Regards,
    Geet

  • 0 in reply to Geet Modi
    Prodigy 230 points
    1. Can you read and share the register value of register 0x0170 after configuring [12:8] as 0x08.
    A:result:0x0c
    2. Which pin you are measuring the clock out ?
    dp83867 pin 18:CLK_OUT
    3. Kindly share the schematics.
  • 0 in reply to michael cao
    TI__Mastermind 26320 points
    0x0170 : 0x0c :
    a) I believe you only sent me higher byte only, lower byte shall be 0x0E
    b) Value of Higher byte as 0x0C : Indicates "01100": Reference clock (synchronous to XI input clock) which is 25 MHz. Matches with your probe on the pin.

    I think, you are not able to program the register properly. Given this register falls in extended register space, kindly refer to section 8.4.2.1 to read/write to these registers.

    Regards,
    Geet
  • 0 in reply to Geet Modi
    Prodigy 230 points
    +dp83867_phy_fixup,CLK_O_SEL:0xc0e
    -dp83867_phy_fixup,CLK_O_SEL:0xe
    my code as following:
    val = phy_read_mmd_indirect(phydev, 0x0170,DP83867_DEVADDR, phydev->addr);
    printk("+%s,CLK_O_SEL:0x%x\n",__func__,val);
    val &= ~(0x1f<<8);
    //val |= (0x4<<8);
    phy_write_mmd_indirect(phydev, 0x0170, DP83867_DEVADDR, phydev->addr, val);
    val = phy_read_mmd_indirect(phydev, 0x0170,DP83867_DEVADDR, phydev->addr);
    printk("-%s,CLK_O_SEL:0x%x\n",__func__,val);
  • 0 in reply to michael cao
    TI__Mastermind 26320 points

    I believe you are not commenting following in your program.

    //val |= (0x4<<8);

    Regards,
    Geet

  • 0 in reply to michael cao
    Prodigy 30 points

    125M CLK is ok, but phy still can't work. (0x0170=0xe，Clock Output Select: Channel A receive clock)

     Is there any other suggestion? Thanks.

  • 0 in reply to Hanfei Zhang
    TI__Mastermind 26320 points

    "125M CLK is ok, but phy still can't work. (0x0170=0xe，Clock Output Select: Channel A receive clock)"

    You mean, you are able to see 125 MHz clock on CLK_OUT.

    Can you please explain the problem you are facing now ?

  • 0 in reply to Geet Modi
    Prodigy 230 points

    now the 100M is ok,but 1000M is not ok.
    [ 32.353548] stmmc_pltfr_fix_mac_speed: fix speed to 100
    [ 32.353597] stmmc_pltfr_fix_mac_speed: fix speed for RGMII
    [ 32.353621] ++++++SET_RGMII_100M+++++++
    [ 32.353644] libphy: stmmac-0:00 - Link is Up - 100/Full
    root@rsb4680:/ # ping 172.21.170.48
    PING 172.21.170.48 (172.21.170.48) 56(84) bytes of data.
    64 bytes from 172.21.170.48: icmp_seq=1 ttl=64 time=1.11 ms
    64 bytes from 172.21.170.48: icmp_seq=2 ttl=64 time=0.506 ms
    64 bytes from 172.21.170.48: icmp_seq=3 ttl=64 time=0.567 ms

    [ 197.450854] stmmc_pltfr_fix_mac_speed: fix speed to 1000
    [ 197.450902] stmmc_pltfr_fix_mac_speed: fix speed for RGMII
    [ 197.450927] ++++++SET_RGMII_1000M+++++++
    [ 197.450950] libphy: stmmac-0:00 - Link is Up - 1000/Full
    1|root@rsb4680:/ # ping 192.168.1.1
    PING 192.168.1.1 (192.168.1.1) 56(84) bytes of data.
    From 192.168.1.2: icmp_seq=1 Destination Host Unreachable
    From 192.168.1.2: icmp_seq=2 Destination Host Unreachable
    From 192.168.1.2: icmp_seq=3 Destination Host Unreachable

    and i enable the tx_clk/rx_clk delay ,my configurations as following:
    val = phy_read_mmd_indirect(phydev, DP83867_RGMIICTL,
    DP83867_DEVADDR, phydev->addr);
    val |= (DP83867_RGMII_TX_CLK_DELAY_EN |
    DP83867_RGMII_RX_CLK_DELAY_EN);
    phy_write_mmd_indirect(phydev, DP83867_RGMIICTL,
    DP83867_DEVADDR, phydev->addr, val);

    delay = (0x7 | (0x5<< DP83867_RGMII_TX_CLK_DELAY_SHIFT));
    phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL,
    DP83867_DEVADDR, phydev->addr, delay);

    val = phy_read_mmd_indirect(phydev, 0x0170,
    DP83867_DEVADDR, phydev->addr);
    val &= ~(0x1f<<8);
    phy_write_mmd_indirect(phydev, 0x0170,
    DP83867_DEVADDR, phydev->addr, val);
    val = phy_read_mmd_indirect(phydev, 0x0170,
    DP83867_DEVADDR, phydev->addr);

    our 1000M rgmii interface's waveform as bmp files

  • 0 in reply to michael cao
    TI__Mastermind 26320 points

    Hi,

    Do you see issues on Rx or Tx path for ping ? Are you able to see your peer receiving the ping command ?

    To configured the delay on RGMII interface, delay introduced by routing on Tx and RX paths has to be computed and additional delays can be introduced using the register 0x0086 as done above. Please refer to below Application Note on how to compute the delay numbers and compute 

    Alternatively, you can try few numbers to see if you get the data going thru the interface ?

    Regards,

    Geet

  • 0 in reply to Geet Modi
    TI__Mastermind 26320 points
    Also, what is the VIO you are using ? It seems around 1.8 v

    Regards,
    Geet
  • 0 in reply to Geet Modi
    Prodigy 230 points
    we modify VIO to 1.8v,its ok,thanks