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DP83822I: Basic register configurations for normal TX and RX operations

Naveen Banad
Prodigy 85 points
Part Number: DP83822I

Hello,

We are using TI DP83822 ENET RMII external Phy in our board. We are doing following configurations to generate 25MHz clock out from PHY to ENET controller.

Software:
1. Phy reset by enabling 15th bit of BMCR register
2. Enabling "RMII Master Mode Reference Clock: 50-MHz" as well as "Clock reference according to bits[14:12]" in "IOCTRL1" register
3. Enabling "25-MHz clock reference, CMOS-level oscillator" as well as"Enable RMII mode of operation" in "RCSR" register

Hardware Connections:
1. Clock source to PHY is 25MHz oscillator
2. RMII PHY is in master mode as mentioned in Page 29, figure 24 of DP83822I datasheet.

Upon configuring above registers Ethernet Link is UP (Auto negotiation is enabled by default in PHY).

But the ping (at u-boot level) to a local host IP address is not happening. We are not seeing ICMP packets coming out from PHY when captured in wire shark.

Do we need to configure any other registers of PHY ?

Thanks,

Naveen B

 

  • 0
    TI__Genius 17990 points
    Hello Naveen,

    Thank you for using the TI forum. Our product expert will get back to you by Thursday.
  • 0 in reply to Mitch M
    TI__Mastermind 18425 points
    Hi Naveen,

    When configuring bit [14:12] of register 0x0462 for 50MHz output, did you configure RX_D3 as clock output by writing '011' to bits [10:8] of the same register?

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 85 points

    Hi Aniruddha,

    Yes, we are configuring both [14:12] and [10:8] bits of 0x462 register. With the confirmation which I had mentioned, ethernet link is up and running when device is connected to a local laptop. But, could not get ICMP pkts on wire.. So, do we need to do any other configurations in Phy ??

    Does this Phy support RMII loop back also ??

    Thanks,

    Naveen B

  • 0 in reply to Naveen Banad
    TI__Mastermind 18425 points
    Hello Naveen,

    Can you check if the RX_D3 pin does indeed output the 50MHz signal? You mentioned that the PHY is configured in RMII mode via register RCSR and not strap. Does the PHY intially power up in MII mode? Can you try adding a digital restart by writing 0x4000 to register 0x1F, after all register initialization is completed on the DP83822?

    To answer your question about RMII loopback, yes the PHY does support MAC side loopback as well as cable side loopback. The loopback modes are controlled via register 0x16[4:0]

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 85 points
    Hi Aniruddha,

    We have proved the pin RX_D3 pin and found generating 50MHz clock. We will try out digital restart.
    Along with this 0x16[4:0], do we need to configure 0x16[5] and 0x00[14] bit ?? Can you plz confirm ??

    Thanks,
    Naveen
  • 0 in reply to Naveen Banad
    TI__Mastermind 18425 points
    Hi Naveen,

    For using the various Near and Far end loopbacks, you only need to set register 0x16[4:0]. Register 0x00[14] will enable the IEEE required MII loopback and register 0x16[5] will program the PHY to transmit data received from the MAC during MII loopback, out on the MDI interface (cable).

    Near End loopback and MII loopback are separate from each other and shouldn't be enabled together.

    -Regards,
    Aniruddha