This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Linux/DP83867IS: Not able to create SGMII link between MAC and PHY

Part Number: DP83867IS

Tool/software: Linux

HI,

We are using K2E SOC having 8 SGMII ports possible. A external PHY (DP83867IS) is connected to SGMII0 which is further connected to Atheros module.

The MDI link (Link between PHY and Atheros) comes up correctly as expected, autonegotiated to 1000Mbit, 100Mbit and 10Mbit against fixed speed counterparts.

However we are experiencing trouble on the SGMII interface.
Reading respective registers in the MAC and the PHY shows that the SGMII autonegotiation process has not completed. No link is established.

Reading MAC regsiter, SGMII_STATUS Status Register (14h), we are getting value 30h, which means nethier autonegotiation is done nor link came up.

Reading Phy register, SGMII Auto-Negotiation Status (37h), we are getting value 0.

RX_CTRL pin on the DP83867IS strapped to mode 3.

Phy Registers Dump.....

mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x0037
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e
0000
0 = SGMII Auto-Negotiation process not complete.
0 = SGMII page has not been received.

mii read 0x03 0x10
5840
TX FIFO Depth 01 = 4 bytes/nibbles (1000Mbps/Other Speeds) ok
RX FIFO Depth ebenso
SGMI_EN 1 = Enable SGMII ok
FORCE_LINK_GOOD POWER_SAVE_MODE 0 = Normal operation ok
MDI_CROSSOVER 1x = Enable automatic crossover ok

mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x06e
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e 
0800
1 = SGMII strapped to enable.

mii write 0x03 0x0D 0x1f
mii write 0x03 0x0E 0x31
mii write 0x03 0x0D 0x401F
mii read 0x03 0x0e 
10b0

mii read 0x03 0x14
29C7
SGMII_AUTONEG_EN 1 ok

Following are the changes done in device tree structure in fle arch/arm/dts/keystone-k2e-evm.dts in U-boot.

ethphy0: ethernet-phy@0 {

status = "ok";
compatible = "ti,dp83867";
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
reg = <0>;
ti,min-output-impedance;

};

Please help me out further in this issue. Please suggest some steps.

Thanks

Prince