• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 33 subscribers
  • Views 787 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DP83867E: Is RX_CLK behaviour in SGMII mode

Roel
Prodigy 200 points
Part Number: DP83867E

Question,

When the device is in SGMII functional mode, is the RX_CLK of the RGMII still alive?

If not, is the SGMII_CO synchronous to the received clock in Slave mode of operation?

Background of the question, I'm looking for a suitable clock to implement SyncE. I could use the CLK_OUT and set it to output one of the received clocks in 1000Base-T mode of operation, but I would like to keep that output for diagnostics.

Roel

  • 0
    TI__Genius 17990 points
    Hello Roel,

    Thank you for using the TI forum. Our product expert will get back to you by Friday.
  • 0 in reply to Mitch M
    TI__Mastermind 18425 points
    Hello Roel,

    The RX_CLK is on during SGMII but I would recommend using CLK-OUT. Does your application need a dedicated diagnostics clock output?

    -Regards,
    Aniruddha
  • 0 in reply to Aniruddha Khadye
    Prodigy 200 points

    Thanks Aniruddha,

    What is the reason you recommend to use CLK_OUT instead of RX_CLK? Because of jitter? I want to use either one of them to be the input clock for a SyncE PLL. Likely the jitter of the RX_CLK is still low enough to generate a clean reference clock.

    I would like to use the CLK_OUT to measure the phases of different clocks, in the hope that I can use it to enhance the precision of the SFD. Especially the master has this +/-4ns timing variation in the SFD_RX, likely I can determine the phase difference between received clock and reference clock as a why to reduce that +/-4ns. At the master side the CLK_OUT would be available for that purpose as I don't need a syncE PLL here, on the slave not as I need to use it to feed the PLL. Still I would like to measure some of the clock phases to understand the behavior of the PHY better. A lot of things are not clear to me, e.g. what the relation is between RX_CLK and all the 4 received clocks. Is the RX_CLK just the one that introduces the largest phase lag?

    And what about the SGMII_CO. I assume that clock is derived directly from the Reference Clock (XI)?

    Roel