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DP83867IS: Communication cannot be setup even in loop back mode

John11513
Expert 5360 points
Part Number: DP83867IS

DP83867IS Design.pdf

Hi,

My customer is designing with DP83867IS. Their MAC connects to PHY through SGMII. Attached file is their schematic. The problem they met is the ethernet link is not very stable. When they PING their equipment through PC some times they cannot get any response. A strange phenomena is it seems the issue is related to the coupling capacitance on SGMII signal line. When they use 0.1uF cap, the condition is the worst, while when they use 100pF it seems the condition is a little better. I also had customer done loopback testing. The problem exist in near end loopback mode. So we think the rootcause is in the design of PHY ckt.

I am not familiar with Ethernet. Could anyone please help me with this problem? 

Thank you,

John

  • 0
    TI__Mastermind 19780 points
    Hi John,

    Thanks for the schematic and information.

    One thing I'd like to confirm is that the RX_CTRL pin for the DP83867 should be set to mode 3, or else the register bits must be changed as per the datasheet. When the register 0x31.7 bit is cleared, auto-negotiation of the link must be restarted.

    In addition, are there any problems with the RGMII PHY being used on the board?

    Can you share the layout for the SGMII routing as well? I see the notes on proper routing are made on the schematic, but I'd like to see if they are followed closely on the layout.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    TI__Expert 5360 points
    Hi Rob,

    Thank you. Yes, you are correct. The issue is partially due to wrong configuration of RX_CTRL which is previously floated. The condition improved significantly once configured to MODE 3 and with 100pf of coupling caps on SGMII interface (basically no packet loss). However, strangely, the link cannot be set up anymore once we changed the coupling caps to 0.1uf. We observed the SGMII signal and found the signal quality is basically same either with 100pf or 0.1uF coupling caps, in which the SOP/SONB signal is good, while SIP/SIN is not very good. I have sent the scope shot of SIP/SIN signal and customer's PCB layout to you through email. Could you please help me take a further look about this issue?
    There is not any issue with another RGMII PHY. They use RGMII PHY only in last design. However, a bug was found in the RGMII interface of MAC. (FPGA integrated MAC) So they have to switch to SGMII. This is the reason why there are two PHYs on their board.

    Regards,
    John
  • 0 in reply to John11513
    TI__Mastermind 19780 points

    Hi John,

    Thank you for the information again.  The routing for SIN/SIP looks less than ideal and may be causing some issues.  The length matching should be done at the mismatch end.  See figure 5 in this high speed routing app note: 

    I would like to clarify that when using 100pF caps, the communications are good?  When you move back to 0.1uF caps, the SGMII link does not work?  Is that true?

    I'd like you to change register 0x31bit[6:5] to 0b00 and try to establish SGMII link with the 100pF caps.

    Best Regards,

  • 0 in reply to Rob Rodrigues
    TI__Expert 5360 points
    Hi Rob,

    Yes, that is true the communications are good when using 100pF caps, while it does not work when move back to 0.1uF. Ok we will try your proposal and feedback you once we get the result.

    Regards,
    John
  • 0 in reply to Rob Rodrigues
    TI__Expert 5360 points
    Hi Rob,
    We have tried your proposal, change register 0x31bit[6:5] to 0b00 and with 100pF caps. The result is basically no change. The link can be established properly with long time withoug packet loss. I am not sure what this test means?
    Thank you,
    John
  • 0 in reply to John11513
    TI__Mastermind 19780 points
    Hi John,

    My apologies. I would like you to use .1uF caps.

    By the way, are the 100pF caps and the .1uF caps the same size? I think you are having a bad reflection in your signal due to the placement of the capacitors on the TX side. The 100 pF caps might present a lower parasitic capacitance and a smaller reflection.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    TI__Expert 5360 points
    Hi Rob,

    In fact I have engineer done the test both with 100pF and 0.1uF caps after register changed as you said. However it seems there is not any improvement. 100pF still work while 0.1uF does not. (100pF and 0.1uF caps are same sized)

    Regards,
  • 0 in reply to John11513
    TI__Mastermind 19780 points
    Hi John,

    You may have an interaction from the layout of the differential traces. The ground plane is poured closely to the diff pair. Usually there is a keepout region around the differential traces of about 3-4 the distance between the traces.

    If 100pF is working for the application, I would stay with it. If they customer is planning a PCB spin, then I'd suggest removing the ground plane in the area around the diff traces and correct the trace length matching.

    Best Regards,
  • 0 in reply to Rob Rodrigues
    TI__Expert 5360 points
    Rob,
    Thank you so much.
    My customer has worked out a new design to close the problem. I have sent the schematic and pcb file to your email. Could you help me review their design? I have not any experience in Ehternet.
    Best Regards,
    John