Part Number: DP83822IF
My customer is using our DP83822. They use FPGA to realize Mac function. Below is the schematic for your check, 4pcs/board.
RP4032-1-001 _ p04-PHY.pdf
They use RMII and 50MHz osc reference.
The problem is that:
1. When debugging DP83822, it was found that the RXDV, RXD[1:0] timing from PHY may have some problem: RXD[1:0] signal will come out 7 clk(about 140ns) after RXDV signal. See below timing picture:
2. These is sudden change at the end of the RXDV's message, see below:
Customer is pushing the pp schedule, so can you help check above 2 questions, thanks a lot!
EFL (Ethernet & FPD Link) Applications Engineer
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with respect to these materials. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.