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DP83822IF: DP83822 timing issue

Part Number: DP83822IF

Hi Team,

My customer is using our DP83822. They use FPGA to realize Mac function. Below is the schematic for your check, 4pcs/board.

RP4032-1-001 _ p04-PHY.pdf

They use RMII and 50MHz osc reference.

The problem is that:

1. When debugging DP83822, it was found that the RXDV, RXD[1:0] timing from PHY may have some problem: RXD[1:0] signal will come out 7 clk(about 140ns) after RXDV signal. See below timing picture:

2. These is sudden change at the end of the RXDV's message, see below:

Customer is pushing the pp schedule, so can you help check above 2 questions, thanks a lot!

Best regards,

Sulyn

  • Hi Sulyn,

    What problem is being caused by the behavior of the RX_DV line? Your schematic looks OK.

    Please read this app note about the behavior of RMII and the RX_DV signal: www.ti.com/.../snla076a.pdf

    That app note is written for the DP83848, but it all applies to the DP83822 as well.

    Best Regards,

    Rob Rodrigues

    EFL (Ethernet & FPD Link) Applications Engineer

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