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  • TI Thinks Resolved

TPD12S016: SDA/SCL_B pin capacitance

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Replies: 13

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Part Number: TPD12S016


We just had some HDMI compliance tests run on our unit which incorporates your TPB12S016.  We failed DDC/CEC Line Capacitance and Voltage.  The Capacitance is too high 650p on SDA  and 950p on SCL. 

While I do not have a LCR bridge that can be set per the test procedure (bias 2.5V, AC voltage 3.5V, Freq 100K) using my LCR bridge (10K, 1V, no bias)  I measure a total Jig+unit capacitance of ~30p without the chip, and 120/190p with the chip (Jig capacitance ~12p). 

We are connected as a sink, SDA/SCL go to port B.  My interpretation of your data sheet shows input C at 15p.  My measured connector/track capacitance is ~18p, so 18p + your 15p  would be 33p and within the speced 50p max...  

Any feedback would be helpful



  • Ed,

    I agree with you interpretation that the pin capacitance of the DDC/CEC

    The only way that I have ever seen a LCR Bridge report a capacitance that out of range is when there was a leaky diode that introduced a voltage/frequency dependent error.

    I cannot see any way that a functional TPD12S016 would introduce 925pF of capacitance. It is also strange that SDA and SCL show significantly different results. The are identical paths within the part, so the cap on both should be the same.

  • In reply to Chuck Branch:

    Do you see anything improper with the way we have the part connected?


  • In reply to Ed Judziewicz:

    Your schematic looks correct to me. The only other suggestion that I can give is to ensure that your ground plane is well connected and that you have good planes with low noise for your power supplies.

    Readings that high on an RLC meter are difficult to explain.
  • In reply to Chuck Branch:

    I finally have the unit we sent in for testing.

    When we measure the capacitance at 20KHz or below.  We get ~30pF which makes sense.  But above say 30K we see a glitch in the stimulus waveform.  See attached.  I think this is probably giving false readings on the test gear.


    TI TPD12S016 100K stimulas 3.5Vp-p, 2.5V offset.docx

  • In reply to Ed Judziewicz:

    This plot might indicate a glitch in the level shifter. It appears that the output driver of the level shifter might be turning on at two thresholds on the input frequency. I can see a few tests that would be useful to run:

    If you run the test at different frequencies, does the glitch pair appear at the same voltage?

    Does the glitch stop appearing above a given higher frequency?

    Have you run the test with multiple units of the TPD12S016?
  • In reply to Chuck Branch:

    For the HDMI test we need to supply a 3.5Vp-p 100K stimulus signal.   

    Since I do not have the "official" setup...  What we did to try and test this was to feed a 7Vp-p, 100K sine, centered on ground through a 1.5K resistor to the I2C pin under test.   This creates a divider via the internal1.5K pull up to 5V and presents a 3.5Vp-p (ish) signal biased at 2.5V.

    We did NOT see the switching feedback glitch at frequencies below 20KHz.  Above 45KHz the signal appears and eventually merges into one pulse above100KHz.

    There is mention of a "rise time accelerator"  How does this impact the test?

    At least two parts responded the same.



  • In reply to Ed Judziewicz:

    I think you are onto something with looking at the rist time accelerator.  I will attempt to contact the design team to get a definitive answer, but  your captures provide good evidence that the LRC measurement is being corrupted by the TPD12S016.

    Can you run the same test where your input sine wave is dc shifted so that the input to the TPD12S016 is always above 800mV.  This should prevent the acceleration circuit from turning on.

  • In reply to Chuck Branch:

    Shifting the sine wave did not have an impact.

  • In reply to Ed Judziewicz:


    Let's try to attack it from the other side. Can you reduce the amplitude and shift the sinewave so that it switches between ground and 650 mV? I am trying to see if we can get a sine wave through that does not trigger the edge rate enhancement circuit.

    I have not yet heard back from the design team.

  • In reply to Chuck Branch:

    Reducing amplitude idi not help

    Any response from the design team?

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