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DP83867IR: RX_CTRL signal voltage levels

Part Number: DP83867IR

Hello,

What are the valid voltage levels of RX_CTRL signal?

I see the following description in datasheet

"the received data available and receive error are combined(RXDV_ER) using both rising and falling edges of the receive clock(RX_CLK)"

I see 1.8v pulses and ~1v pulses on this pin. Does 1.8v pulses correspond to valid packets? Does 1v pulses mean RX_ER?

Thanks,

Sanjeev Karaiyan

Sanjeev Karaiyan

  • Hi Sanjeev,

    The RX_DV logic level is presented on the rising edge of RX_CLK.  The RX_ER logic level is presented on the falling edge of the RX_CLK.

    From the RGMII v2.0 spec:

    You should not see 1V pulses.  This means something is wrong with the PHY, the MAC, or the probing of the signal lines.

    Best Regards,

    Rob Rodrigues

    EFL (Ethernet & FPD Link) Applications Engineer

  • In reply to Rob Rodrigues:

    Hello Rob,

    I want some clarification on the case of receiving a valid frame with errors. Does the RX_CTRL signal keeps on toggling every edge of the RXC clock for the entire duration of the frame?

    More observations on the 1V pulse issue:
    1. I replaced the probes and scopes with higher bandwidth versions. Still same behavior is seen.
    2. The 1V pulse issue on RX_CTRL is not seen for every received frame. It occurs for random frames (so far couldn't find any pattern)
    3. The issue sometimes starts in between reception of a frame such that the 1.8V level jumps down to 1V. Sometimes it occurs for entire duration of a frame.
    4. I could see this issue in different boards also. So not a board fault.

    Thanks,
    Sanjeev

    Sanjeev Karaiyan

  • In reply to Sanjeev Karaiyan:

    Hi Sanjeev,

    No, the RX_CTRL signal only toggles on the errored byte. If you are seeing constantly RX_CTRL toggling, then you have something wrong with your HW, or your link partner has a very high amount of jitter.

    Do you have a schematic you can share?

    Best Regards,

    Rob Rodrigues

    EFL (Ethernet & FPD Link) Applications Engineer

  • In reply to Rob Rodrigues:

    Hello Rob,

    This problem is seen with PHYs on industrial ethernet daughter card of AM654x IDK. www.ti.com/.../tmdx654idkevm

    Thanks,
    Sanjeev

    Sanjeev Karaiyan