Part Number: DP83867E
Can't seem to figure out why device is unable to function properly.. Reviewed voltage levels and clock, all appear to be within datasheet parameters. Replaced device with new one and still same results. Any idea what would cause such behavior?
EFL (Ethernet & FPD Link) Applications Engineer
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In reply to Rob Rodrigues:
Thank you Rob for getting back to me. I didn't see that in the data sheet as a potential problem.
In reply to Darryn Long:
Thank you for your feedback Rob.
RBIAS did have an incorrect resistor installed, but we caught that earlier.
The 125MHz clock is a typo. It is 25MHz.
We have three PHYs, so the 9k internal pulldown on each chip creates a 3k pull down on the signal line...correct?
Those two signals are being routed to a CPLD (Altera Max5) device, which is being used as a voltage translator. (+1.8V --->+3.3V).
Their outputs go to a connector where they are unused. I'd have to review the designer's code to see if they're being driven at all.
We contracted out this design and I'm trying to figure out the problems and solve them, so I really appreciate your help!
Sorry Rob, I misread the schematic.
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