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TLK10034: 10G Base-KR AUTO NEGOTIATION is not getting completed with External Switch.

Prodigy 90 points

Replies: 12

Views: 281

Part Number: TLK10034


In our design we have used TLK10034 in (XAUI <-->10G Base-KR mode), 4x 10G Base-KR channels are connected to an External Switch (residing on the same PCB). 4x XAUI channels are connected to a XAUI switch. The 4x XAUI channel links are UP. But 10G Base-KR side link is not UP. Auto Negotiation is not completing with value of AN_STATUS register (0x7.0x1) toggling between 0x88 and 0xCD .The Auto Negotiation is not completed on the Link Partner side also.

What might be causing this?

  • In reply to NARENDAR REDDY VYR:

    Hi Narendar,

    Unfortunately we are limited in the support provided for this device issue. I can say that the toggling is caused by link drop in auto negotiation. Device appears to be reporting LOS condition which is only possible if the criteria in the data sheet are met.

  • In reply to Malik Barton57:

    Hi Malik Barton,
                    Some more updations &  observations regarding 10G base KR with 10GKR auto-negotiation happening at Jaguar2 chip side(L2 Switch.i.e LP).
    We have started vitesse appln and 4 x 10GbaseKR interfaces were configured. We gave a reset to TI device and 10GKR auto-negotiation is completed at the Jaguar2 chip side(L2 Switch.i.e LP). The observation of AUTONEG register and training registers are compiled in the excel sheet for your information which is attached with this mail.
    LP_ADV registers at TI PHY device is not getting updated and here is the dump below.
    JR2 register dump :  Auto neg  registers set LD_ADV  & LP_ADV
    XGKR1[0]:LD_ADV:KR_7X0010 0x00001001
    XGKR1[0]:LD_ADV:KR_7X0011 0x00000000
    XGKR1[0]:LD_ADV:KR_7X0012 0x0000c000
    XGKR1[0]:LP_BASE_PAGE_0:KR_7X0013 0x00005361
    XGKR1[0]:LP_BASE_PAGE_1:KR_7X0014 0x00000083
    XGKR1[0]:LP_BASE_PAGE_2:KR_7X0015 0x0000c000
    TI-10GbaseKR PHY device register dump:   LD_ADV & LP_ADV.

    0X0007 10 0X1001 R/W 0X1001
    0X0007 11 0X0080 R/W 0X0080
    0X0007 12 0X4000 R/W 0X4000
    0X0007 13 0X0001 RO 0x0001
    0X0007 14 0X0000 RO 0X0000
    0X0007 15 0X0000 RO 0X0000

    why is register 0x13, 0x14, 0x15 not updated on TI PHY with JR2 LD_ADV values. ?
    Any hints of 10G KR AUTONEG register settings to be done at both ends so that 10gkr autoneg completes at TI PHY side also?

    I think, if this happens, autoneg process will be completed followed by link training and link UP.
    Any suggestions regarding solving this issue is welcome.
    [NOTE: Attaching excel sheet of all relevant register dumps along with data sheet]