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[FAQ] TDP142: How do I debug the issue of a monitor having no display?

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Part Number: TDP142

I have a DP monitor that does not display, how do I debug this issue?

  • For DisplayPort, there are three major components: the main link, the AUX channel, and the Hot Plug Detect or HPD. When debugging the issue of a monitor that has no display, we need to take a look at each component.

    1. Please check and make sure HPD is driven high (3.3V). HPD is a 3.3V signal provided by the sink to the source. For DP, HPD serves two purposes:
    a. HPD serves as sink presence and absence notification. When HPD is high or 3.3V, this indicates the presence of the sink. When HPD is low or 0V for greater than 2ms, this indicates the absence or the removal of the sink.
    b. HPD serves as an interrupt from the sink to the source. When HPD is low or 0V between 0.5 to 1ms, this indicates an interrupt event, a sink request to the source to read the sink’s DPCD register.

    2. The main link is used for transmission of video and audio. Electrical compliance test should be ran on all the lanes of the main links to verify each lane passes the electrical compliance test. For source, this is accomplished by the DisplayPort transmitter electrical compliance test. For sink, this is accomplished by the DisplayPort receiver jitter tolerance compliance test. Source swing/pre-emphasis level and redriver equalizer need to be tuned to achieve the optimal system performance.

    3. AUX communication starts when a sink is plugged (HPD = 3.3V). The source reads the sink’s EDID for the supported video mode and sink’s DPCD for the supported data rate and lane configuration. Once the EDID and DPCD have been read, the source starts the link training. The link training consists two phases: a clock recovery phase and a channel equalization phase. During these two phases, the sink reports the received signal quality and request the desired signal amplitude and pre-emphasis level. The source updates its PHY amplitude and pre-emphasis level base on the sink request.

    The clock recovery phase is completed when the clock recovery flag is set and the link training moves onto the channel equalization phase. The channel equalization phase is completed when Channel Equalization, Symbol-Lock, Inter-lane Alignment flags are all set.

    An AUX monitor can be used to capture the AUX communication. Pay attention to the data rate and lane configuration and make sure the source/sink are correctly communicating the data rate and lane configuration. Once the data rate and lane configuration are set correctly, take a look at the clock recovery and channel equalization training phase to see where the issue is. If clock recovery and channel equalization training phase fail at higher data rate or four lane configurations, try with lower data rate or one/two lane configurations.

    Best Regards
    David

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