Part Number: DS80PCI800
We are designing a Board-to-Wire PCIe GEN3.0 x8 connection. The PCB trace length is about 10000mil(10inch), and cable length is about 0.5meter.
Someone thinks both the length of PCB trace and cable are too long, Signal Integrity(SI) might be an issue, and we may need a PCIe redriver (repeater) inserted into the signal path.
(1) Is there maximum PCB trace length, or cable length , or total signal path length requirement for PCIe ?
(2) Under what circumstance should we use a PCIe repeater like ds80pci800 ?
These may be general questions, but any comments are appreciated ! Thanks.
1. There is no specific length maximum. Mostly the system will be limited by transmission losses. The maximum loss used in systems is given by the calibration channel guidelines in the PCIe base specification. For Gen3 the calibration channel loss is listed at 20-22 dB @ 4 GHz. Typical losses in Gen3 systems are just under 1 dB/inch. High performance board material will reduce the loss and allow for longer transmission distance.
2. We recommend to look at repeaters as the worst case loss approaches the 20 dB level. For Gen3 systems the DS80PCI800 and DS80PCI810 repeaters are most often used in systems with 20-30dB of attenuation. Certainly above 35dB customers are looking to architect a retiming element (PCIe switch or retimer) into the channel.
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In reply to Lee Sledjeski:
Is TI have any doc for PCIe Gen3.0 layout guidelines? Not sure whether AC caps should be placed near TX IC or near connector. And other general guidelines are welcome.
In reply to yi xiao:
I do not have a specific document for layout. When I review layouts here are the recommendations I make most often.
1. Place the AC caps closer to the PCB connecter, away from the Tx IC pins. This allows any reflected energy time to dissipate within the transmission line and have little impact on the signal jitter content.
2. Use 85 Ohm differential traces for PCIe applications.
3. Use 0201 size AC coupling capacitors with a value of 0.22uF for PCIe applications.
4. If 0402 size AC coupling capacitors are used, they will benefit from a GND relief directly below the capacitor footprint. This is especially true as the dielectric thickness used in the adjacent PCB layter is < 5mils.
5. The DS80PCI800 high speed pads will benefit from a GND relief as well, especially true as the dielectric thickness used is < 5mils.
6. Match the intra-pair length of signals.
7. Invert routing of P/N signals as needed to create the best layout. PCIe components can internally invert the received signal.
Thanks for answer. some questions to consult.
1. Our situation is, if we put AC caps near connector , we have to add one more pair of trasinstion-layer vias than the situiation when caps near IC . Seems hard to choose. Personally I think the caps should be ok to be placed near IC, ,what's more, I think vias are more detrimental than locations of caps. How do you think?
2. For your poitns 4/5, I searched some tech note, and indeed found there is recommnedation that "cut the GND under the AC caps", I think this is what you refer as "GND relief directly below the capacitor footprint". Could you plesea expalin why this method helps better signal quality?
Thanks again !
referance note: www.intel.com/.../tb-095.pdf
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