Part Number: SN65DSI85
For MIPI input, customer's DP to MIPI bridge IC is designated for to two separated LCD for left & right eye, so that there is a skew(tSK) 1.88us between mipi port 00 & mipi port 10
May I know if it is ok for SN65DSI85?
If that is less than 9 DSI HS clock cycles as the image depicts, then it should be fine.
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In reply to I.K. Anyiam:
Thanks for your reply.
But since customer project is dual panel 1280*720, with DSI clock cycle is around 4.4ns.
Their DP to MIPI bridge IC skew could achieve 1.88us which is larger than 9*cycles…
What would be the risk for this ? Anyway to solve or improve it?
In reply to Antony Lin:
They should try and reduce the skew so that it is within datasheet recommendations. 1.88us is very excessive.
May we know what could the exactly application issue from such a long skew? No display? Display with lots of noise.....?
It can result in those display anomalies, yes.
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