• Resolved

DP83822I: RX_CLK pulled low during reset

Prodigy 30 points

Replies: 5

Views: 103

Part Number: DP83822I

I use DP83822 in design with AM3358 as PRU PHY.

In Datasheet page 8 is : During RESET: RX_CLK on pin 25 is output O with PD.

It means Output active LOW?

After the power up, this line is used  to configure our Sitara.(LCD data 14) Therefore his circuitry did not work, because our device drives this pin to ground.

Is there any recommendation, how to overcome this behavior?

"After power up the system, our device pulls the pin 25 RX_CLK to low, even if my customer adds a 1kOhm pull up resistor to the line.

This is completely different to the behavior from our TLK105."

Best regards,

Jiri

  • Hi Jiri,

    Which device powers up first ? PHY or Sitara ?  What state you need this pin ? You can isolate this pin by using MII Isolate.

    Regards,

    Geet

     

  • In reply to Geet Modi:

    Hi Geet,

    As power chip is used TPS65217C  PHY is powered from LDO4. Sitara starts after  Power_good (PWRONRST),  so PHY start first. PHY RST is GPIO but during RST is MII_RXCLK output active low.

    MII Isolate is not usable because default is not isolated and for set to isolate I need boot Sitara.  SYSBOOT is set for 19.2MHz and I need 24MHz (MII_RXCLK is LCD14).

    Thanks,

    Jiri

  • In reply to user448712:

    Hi Jiri,

    Can you try using IEEE Power Down thru PIN while PHY in reset ?

    Regards,

    Geet

  • In reply to Geet Modi:

    Hi Geet,

    Power down seems good, but it is not well documented in datasheet.

    is somewere table like:

    "Table 1. IO Pins State During Reset"

    but about power down?

    Regards,

    Jiri

  • In reply to user448712:

    Hi,

    During Power Down : Output IOs will stop driving. 

    Regards,

    Geet