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  • TI Thinks Resolved

SN65DSI86: 10/8 bit HDR Support

Prodigy 220 points

Replies: 5

Views: 127

Part Number: SN65DSI86

Hi Team,

We have a requirement for 4K@60fps eDP with 8/10 bit HDR support. We are planning to convert two 4 lane DSI1.2(2.1 Gbps per lane) to eDP 4K@60fps using SN65DSI86 bridge IC.

May I know whether SN65DSI86 support 8/10 bit HDR?

Thanks & Regards,

Gireesh

  • Gireesh

    For DSI86, the dual-channel DSI receiver configurable for one, two, three, or four D-PHY Data Lanes per channel operating up to 1.5 Gbps Per Lane. 2.1G per lane is outside the max 1.5G supported data rate and can't be supported by the DSI86.

    Thanks

    David 

  • In reply to David (ASIC) Liu:

    Hi David,

    Thanks for the prompt reply,

    2.1 Gbps per lane is the maximum capability of the D-PHY controller on SOC. we will use dual-channel DSI at 1.33Gbps per lane (<1.5Gbps per lane) to achieve 4K@ 60fps eDP.

    May I know whether eDP at 4K60fps with 8/10 bit HDR is supported on SN65DSI86?

    Regards,

    Gireesh

  • In reply to Gireesh Nair40:

    Gireesh

    Please see attached app note: http://www.ti.com/lit/an/slla425/slla425.pdf. Please use this app note to calculate the requirement.

    For the DSI86, we can only support 4k@60Hz 18bpp, but not 24bpp.

    Thanks

    David

  • In reply to David (ASIC) Liu:

    Hi David,

    Thanks for the input.

    Our knowledge on HDR Technology is preliminary. Based on the information we have gathered from VESA website( displayhdr.org/.../ ), we understand that it requires a minimum of 24bpp to support HDR. We also understand from your inputs for our resolution and frame rate requirements (4K@60 Hz) SN65DSI86 can support only 18bpp. Would it be correct to say that HDR cannot be supported for this requirement?

    If we had to scale down our resolution and frame rate requirements to something lower that can be supported by 24 bpp, would HDR then be supported with SN65DSI86?

    May I also request you to confirm if HDR as a feature has been validated with the SN65DSI86?

    Regards,
    Gireesh

  • In reply to Gireesh Nair40:

    Gireesh

    The Stream_Bit_Rate = Pixel Clock x BPP, and

    Min_Required_DSI_CLK_FREQ = Stream_Bit_Rate / (Min_Number_DSI_Lanes x 2)

    Knowing the particular Pixel Clock frequency and BPP of the resolution you want to support, you can then use the above two formulas to calculate the minimum DSI clock frequency and make sure it does not violate the maximum DSI clock frequency.

    Thanks

    David

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