TUSB1210: EMI concerns from USB and ULPI clock rates
Part Number: TUSB1210
I have very little control over the TUSB1210 USB PHY in terms of EMI/EMC. I am using a Xilinx ZYNQ device to communicate over ULPI running at 60 MHz. My customer is testing our board in their setup. They failed FCC Rule 15. I am asking the customer to just test Full Speed instead of High Speed to see if the problem areas move around relative to the USB data rate. Since I have very little control at this device level, I am looking for options that might help reduce the EMI/EMC. I didn't see any slew rate items in the memory map. I see in the datasheet in Section 4.1 (Datasheet revised August 2012) that the USB PLL generates both the 60 MHz ULPI and the USB data interface rate (480 Mbps). I use a 24 MHz clock from the FPGA to feed the TUSB1210.
In reply to Bill Whitehead:
The 60 MHz ULPI clock is an output of the TI part. I don't see anything that would allow me to change or modify the slew rate. Are there any options to do that when the TI USB PHY is the driver on the 60 MHz ULPI Clock?
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sorry, you can change slew rate of 60Mhz,
In reply to Brian Zhou:
I assume you meant, I cannot change the slew rate. That is what I assumed, but wanted to verify. I didn't see any controls that would allow that.
sorry, you are right.
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