• TI Thinks Resolved

TLK10031: About TLK10031 register setting for XAUI to SFI/XFI

Intellectual 320 points

Replies: 9

Views: 284

Part Number: TLK10031

Hi

Could you let me some advice for XAUI to SFI/XFI?

I already referred to https://e2e.ti.com/support/interface/f/138/p/760354/2852936?tisearch=e2e-sitesearch&keymatch=TLK10031#2852936 in order to configure XAUI to XFI.

But LS_PLL_LOCK and HS_PLL_LOCK field indicated PLL-unlock.

So I'd like to get some advice about setting up. while debugging problem, I dobule checked hardware strapping for 10G-KR( MODE_SEL, 1E.0001 bit 10 in accordance with Table 7-2).

Current MODE_SEL is set to PD.

Q1) CHANNEL_CONTROL_1  :

 the default value of This register is 0x0B24. What is right value  of  SW_PCS_SEL &  SW_DEV_MODE_SEL for XAUI to XFI/SFI? I tried 0x324 or 0x724 to CHANNEL_CONTROL_1 

Q2) HS_CH_CONTROL_1 (register = 0x001D) (default = 0x0000) (device address: 0x1E)

According to the description of bit [13:12], REFCLK_FREQ_SEL_1,REFCLK_FREQ_SEL_0,  HS_PLL_MULT,LS_MPY field on 1E.0002, 1E0003 must be set up automatically.

when I read two register, HS_PLL_MULT field had 0xD. but Accoriding to Table 7-1, It should have 0xC for 16.5 multiplier.  Do you think which one affected  default vaule of HS_PLL_MULT(0x0D)?

When user wants to apply manual setting according description on REFCLK_FREG_SEL1, Is there any specific necessary sequence?

Q3)  Does link status on HS, LS Interface affect LS_PLL_LOCK and HS_PLL_LOCK 's value?

appreciate your help in advacne.

thank you

Best Regards

  • Hi,

    First off, the LS and HS settings for XAUI-to-SFI and XAUI-to-KR are the same. From a PHY configuration perspective the one difference is that link training and auto-neg should be disabled when operating in SFI mode (vs KR.)  I would recommend to check the following:

    • MOD_SEL pin should be set high, for fixed 10G rate operation on HS side
    • LS and HS sides line rate and reference clock selection setting for 10G KR are used, as per Table 7-1 (included below for ease of reference)
    • LT_training_enable bit should be set to zero
    • Table 7-1. Specific Line Rate and Reference Clock Selection for the 10GBASE-KR Mode:

      LOW SPEED SIDE

      HIGH SPEED SIDE

      Line Rate

      (Mbps)

      SERDES PLL Multiplier

      Rate

      REFCLKP/N (MHz)

      Line Rate

      (Mbps)

      SERDES PLL Multiplier

      Rate

      REFCLKP/N (MHz)

      3125

      10

      Full

      156.25

      10312.5

      16.5

      Full

      156.25

      3125

      5

      Full

      312.5

      10312.5

      8.25

      Full

      312.5

    See below related to the questions,

    1. Default should be ok for CHANNEL_CONTROL_1 except for LT_TRAINING_CONTROL which I would recommend to set to 0
    2. the default values for HS_CH_CONTROL_1 should work for your application. For your case, REFCLK_FREQ_SEl_0 should be set to 0
    3. Yes

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • In reply to Rodrigo Natal:

    Hi Rodrigo Natal

    appreciate your prompt answer.

    I have two questions more

    From your comment, TLK10031 should be operated after applying register setting on https://e2e.ti.com/support/interface/f/138/p/760354/2852936?tisearch=e2e-sitesearch&keymatch=TLK10031#2852936

    First question, Regarding MOD_SEL , you recommend that MOD_SEL pin should be set high, for fixed 10G rate operation on HS side.

    But Table 7-2 describes it should be low as below table. which one is right?

    Second qustion is what is expected value on HS_PLL_MULT when REFCLK_FREQ_SEL_1 is set to be b'0. As I wrote, I expected it as 0xC. but  read value was 0xD.

    thank you

    Best Regards

    Mark Kim

  • Hi

    In order to check if TLK10031 was  operated normally or not, I set powerdown on PMD, PCS and adjusted SWING level.

    But  Regardless of setting, output level of HS interface was kept a same output status. in other words, the powerdown and swing level setting were not applied as expected.

    so  I would like to aske your schematic reiew which is attached.

    Basically, I reviewed basic strapping based on datasheet and   Bring Up Procedures which is targeted to TLK10232 togther with Linked question on E2E.

    Please review the attached schematic.

    Basically, I referred to below comment on the attached application note (page 11) for xaui to xfi together with comment on e2e site, except for REFCLK_SEL

    Set in KR manual mode with Auto Negotiation and Link Training off
    • Device Pin Settings
    o Ensure ST input pin is Low
    o Ensure MODE_SEL input pin is Low
    o Ensure PRBSEN input pin is Low
    o Ensure REFCLK_SEL input pin is Low

  • In reply to YoungYun Kim:

    Hi,

    • Which clock inputs are actually being used, REFCLK0P/N or REFCLK1P/N? It's hard to tell from the schematic. The unused REFCLK inputs should be pulled down to GND through a shared 100 Ω resistor.
    • if MOD_SEL pin is set low then AN_ENABLE should be set to 0 for XAUI-to-SFI mode 

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • In reply to Rodrigo Natal:

    Hi Rodrigo Natal

    I am sorry for many questions. But I need your help so as to verify if TLK10031 is operated normally or not.

    As I wrote, I 0272.0755.tlk10232_BringupProcedures_v2.pdfreferred to a couple of e2e ticket for bring up or initiliaztion of TLK10031 in addition to Bring Up Procedures (the attached applicatio note )

    I believe I figured out register setting guide on e2e ticket and the application note well.

    But unfortunately, I didn't faced expected operation. Please let me have your commnet for below questions.

    1) 0x1e. 8020 register

    one of register setting TI has recommended is to set 0x3ff on 0x1e.8020. But I can't relevant register information on datasheet.

    So I went through a few datasheets and found a related Register in TLK10034.

    Q)  Ask for confirmationon if  TLK10031 also has the same Register field.

    2) Failed to control power down and Swing level on HS.

    In order to check if register setting was applied as well, I tried to power down on PMA/PMD Registers or PCS register, CHANNEL_CONTROL_1.

    After applied Power down through one of them, I tried it without or with data path reset.( 0x1e.000e )

    Furthermore, I also tired to chnage swing level on HS via 0x1e.0003( HS_SERDES_CONTROL_2)

    --> Consequence was that Output on HS didn't change at all.
    Regardless of trial( Power down, Swing control), the HS output remained in its initial swing state.

    Q) is there recommend sequence to control swing by the above registers?

    Q) Please help what I should do in order to check if chip is normal

    thank for kind help in advance.

    Best Regards

    Mark Kim

  • In reply to YoungYun Kim:

    Hi,

    It is not clear to me whether basic MDIO communication to the PHY is successfully happening on your system board. Can you read a few PHY STATUS registers and confirm that you are able to observe the default bit values as per the datasheet? if possible please provide a full TLK PHY chip status registers values dump.

    I would recommend to focus on the TLK10031 datasheet as your point of reference to avoid confusion.

    Cordially,

    Rodrigo Natal

    HSSC Applications Engineer

  • In reply to Rodrigo Natal:

    Hi

    For CL45 operation verification , as first step , I read PHY Identification value  which is fixed and other registers to compare dump value with  default value.

    and As second step, write values on several registers and read them back for written value comparision.

    I didn't find any problem on CL45 operation.

    Anyhow, I will update chip status registers values.

    Best Regards

    Mark Kim 

  • In reply to YoungYun Kim:

    Hi Rodrigo Natal

    We found what caused the above problem. but We still want to take your confirmation for device 0x1e register 0x8020.

    Could you please confirm if TLK10031 has the same register infomraion with TLK10034.

    We just want to take your confiratmon about that register fileds on Device 0x1e register 0x8020 exist on both TLK10031 and TLK10034.

    Below description is copied from TLK10034 ( register address : Device 0x1e, register 0x8020). But two devices have different default values on datasheet.

    Please help me clarify 0x1e register 0x8020.

    thank you

    Best Regards

    Mark Kim

  • In reply to YoungYun Kim:

    Hi,

    0x1e register 0x8020 is RESERVED on the TLK10031.

    Regards,

    Rodrigo Natal