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Part Number: PCA9306
To allow proper translation of I2C signals from one voltage reference to another, both the high-level and low-level voltage thresholds need to be translated. However, these threshold voltages are not mentioned in the datasheet of the PCA9306. Are you able to provide the calculations for both the high-level and low-level voltage thresholds when receiving data into the PCA9306, and also the calculations for the transmitted data high and low levels?
The PCA9306 is a pass gate device so it does not have a tradition Vil, Vih, Vol, Voh specifications. The pass fet gets turned "ON" when the input goes below a Vth of the Vref1 voltage. That is true for either side of the device. When the FET turns "OFF" the FET is high impedance and the pull-ups on both sides pull it up to each respective voltage rail. The Vol will be dependent on the pull up resistor, the pull-down FET resistance (either master or slave side), and the series resistance of the PASS FET.
I have entered a link to a previous post that explains how the device operates. Please feel free to do more searches on E2E using the search bar at the top of the E2E forum to search for previously asked and answered questions.
If it still isn't clear, then please let me know and I will help answer any other questions you might have.
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In reply to fhoude:
We have an application where there is a 300ohm fixed resistance on the line between the PCA9306 (3.3V side) and the I2C device. There is direct connection between the PCA9306 (1.8V side) and the other I2C device. All other circuitry is as recommended by TI.
I looked at the other post you recommended, and I have to say it is rather confusing. It seems the voltage level explanation tries to use the FETs of both I2C devices, but actually if that were the case then there would be current flow between SDA1 and SDA2, in which case there would be a voltage divider between the 1.8V and 3.3V supplies. Of course this doesn't make sense for a level translator, so the proper explanation should only consider one side of the PCA9306 when working out the voltage levels, there should be minimal current flow between SDA1 and SDA2 - perhaps a current mirror is used?
Could you please help provide the equivalent circuit of the SW block inside the PCA9306, and the value range of Vth for both Vref1 and Vref2? I'm sure we can work out what's happening in the application if TI can provide this information.
In reply to Simon Arthur:
I think what is confusing for you is that the pass FET is only on during the LOW period. As the SDA/SCL line is released from low state, the pull up raises the voltage and the FET gets turned off, thus no voltage divider. The PCA9306 creates a reference voltage as seen below and that is used to control the PASS fets. Let me know if this isn't clear.
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