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LMH0071: LVDS Decode verilog fpga software question

Part Number: LMH0071
Other Parts Discussed in Thread: LMH0340, LMH0341, LMH0070

I've compiled the Altera fpga code ( NSM_SINGLELINK ) but it's made for a CycloneIII and I've got a NAX10 so I don't know if I've mistranslated the PLL or desializer or something... OR if there's a trick to making the LMH034- based fpga code work with the LMH0071.

I CAN FIND NO INFORMATION ON HOW THE 5-BIT DATA BUS ( lvdsTX[4:0] is to be compiled into the 20-bit pre-descrambler bus.

I suppose I could trial and error the 5-bit code order but it would help if I knew something about the 5-bt words inter-relationship
Do SYMBOL N and SYMBIOL N + 1  combine into a single 10 bit word ?

Or do SYMBOL N+1 and SYMBIOL N+2  combine into a single 10 bit word ?

Where does the upper 10 bits come from in the LMH0071 ?

There only 10 bits of data coming across the bus at 27MHZ yet the 'ipt_rx_io_altera" module puts out a 20 bit bus !!

Is the upper 10-bit word a dulicate?

is it needed?

Is there ANY DOCUMENTATION ANYWHERE WHICH ACTUALLY ANSWERS THESE VERY BASIC QUESTIONS ????

Thanks

  • Hi Rob,

    The LMH0340/0070 and LMH0341/0071 devices at their core are simple serializers and deserializers. Therefore, if you know the format of the data coming from the source FPGA to LMH0070 that is then serialized and driven to the LMH0071 input, the LMH0071 should deserialize with the equivalent mapping of how it was serialized in.

    The typical mapping for the 5-bit word coming from LMH0071 input to LVDS output is as follows:

    The LMH0071 is agnostic to the exact definition of each bit it receives. It is up to the FPGA after the LMH0071 to identify and interpret the correct mapping that is consistent with how the data was serialized. Typically the descrambler will need to perform a reverse polynomial specified by the respective standard, and this processing may be better answered by the FPGA vendor. We have limited knowledge to answer your question about how to compile the LMH0071 output in the 20-bit pre-descrambler bus, since our lead engineers who worked on co-developing IP for our LMH0340/0341 reference boards are no longer at TI.

    I would recommend checking with Intel/Altera to see if they have any suggestions.

    Michael

  • Thanks, that's exactly what i needed !!