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TLK10232: 10GKR HS ERROR

Part Number: TLK10232

Hi,

We use TLK10232 chip in the following configuration:
(1) LS_side
    Altera FPGA (XAUI 3.125MHz 4lane) => TLK10232
(2) HS_side
    TLK10232 (1lane 10G-KR) => opt.SFP module => optic Cable => opt.SFP module => TLK10232 (1lane 10G-KR)

When our PCBs operate with this particular chip, we faced the following problem: after initialization and reaching normal operative mode , HS FEC Correctable Error sometimes appeared. (Reg Addr:0xAC、Dev Addr:0x01)
・Error occurrence frequency changes in every off/on.  For example, error occurs 10 times per minute and we power off/on PCBs , initialize normal operative setting ,then, error occurs 10 times per day.
・Error occurs in NOT ALL PCBs. Error occurs in some serial numbers.
・The Low speed side is always good.
・Length of traces from TLK10232 to SFP module is less than 20mm . (No vias or stubs)

We use this chip in 10GKR FEC Mode and following is initiation setting.
1. Reset device (assert RESET_N and PDTRXA_N pins)
2. Make sure the reference clock selection  – we use 156.25 MHz ,so no register changes.
3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
4. Disable link training by writing 16’h0000 to 0x01.0096
5. Write 16’h03FF to 0x1E.8020.
6. Write HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.
7.    Write 16’h0003 to 0x01.00AB - Enable 10GBASE-R FEC
8. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.
9.    Clear Latched Registers (including 0x01.00AC)

We used information from the following :
e2e.ti.com/.../1833175
tlk10232_BringupProcedures_v2.pdf
tlk10232.pdf
4520.TLK10034_link_training_app_note (10).doc

★We don’t understand the cause of HS errors and why sometimes(some chips) error occurs and don't occurs . Please can you help us!

12 Replies

  • In reply to Luis Omar Moran:

    Hi,

    We have not sloved this problem yet.

    We are trying tuning registers but we have not found setting in which 10G errors don't occur.

    So if you have any advice to improve 10G signal quality, could you tell us?
    For example, PCB Layouts or power-supply voltage or tempreture or etc.

    We will try any adivice to slove this problem.

    Regards,

  • In reply to user499018372:

    Hello,

    Could you provide your schematics and layout to review them?
    omar.moran@ti.com

    Thanks,
    Luis Omar Moran
    High Speed Interface
    SWAT Team

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