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DS90UB953-Q1: does DS90UB953-Q1 I2C master supports clock stretching?

Part Number: DS90UB953-Q1

hi,

i am trying to access a remote slave which requires clock stretching using one I2C transaction.

meaning by initiating I2C transaction from Host --> DS90UB9534--> DS90UB953 --> remote slave  (clock stretching mechanism activated by remote slave)  --> slave of remote slave.

i fail doing this test, i assume that DS90UB953 I2C master doesn't supports clock stretching. 

is it correct?

  • Hi Tomer,

    From your question, it seems like you are having difficulty communicating with the remote slave.

    Please verify that you have set the serializer alias (954 register 0x5C), slave ID (954 register 0x5D), and slave alias (954 register 0x65).

    Before changing these, make sure to select the desired 954 port in 954 register 0x4C.

    Regards,
    Zoe
  • hi Zoe,

    i am not sure my question was described properly, please let me clarify.

    i can access a given remote slave by the given I2C commands: Host --> 954 --> 953 --> REMOTE slave.

    But when I try to access to a slave of the remote slave: Host --> 954 --> 953 --> Remote slave --> slave of the remote slave --> meaning remote slave working according to clock stretching mechanism (remote slave asserts clock stretching for the 953) path seems to be broken. 

    thefore my conclusion is that I2C master which is instantiated inside the 953 doesn't support clock stretching.

  • Hi Tomer,

    Thanks for the clarification. The 953 should support clock stretching.

    I have a few things to try to figure this out:

    1. Verify the SCL timing is chosen to match an I2C mode supported by the slaves (register settings on the 953)
    2. Verify you have assigned an ID and an alias for the second slave in the 954 and 953 registers
    3. Try increasing the BCC watchdog timer on the 954 to aid in debugging

    As well, a capture of the I2C traffic during this time may help figure out what's not working. Is the I2C actually getting to the remote slave and no ACK is given back to 954? The 953 should give Nack if so.


    Regards,

    Zoe

  • aHi Zoe,

    Thanks for your support, first of all let me refer to your inputs:

    1. I am not sure it is timing issues, since regular wr/rd commands from 954 are functioning well. anyhow, can you be more specific which registers should be configured? do you think it is hold violaition? i am a bit confused.

    2. I am sure it is not configuration issue since same commands behaves correctly over different elemets (see detailed description below).

    3. i have disabled BCC wathcdog timer.

    i have attached to this mail wavefrom from scope that shows the problem. this transaction is read transaction that tries to read from 953 (ALIAS ID 20, offset 0x00) connected through FPD to 954. you can see that transaction behaves extremely strange --> it can be seen that 954 provides ACK although he should operate clock stretching mechanism (problem seems to be related to this specific 954), and read command is stuck at some point.

    full: I2C transaction:

     

    ID part zoom (0x20 alias ID)

    offset zoom (address 0x00)

    read part:

    after i have recognized that the problem is due to 954 strange behavious i have tried the same test over different element (954) inside the system and It seems to be working --> as you said 953 supports clock stretching :),  Anyhow, any ideas why this specifc 954 elements behaves strangely? timing (althugh regular I2C commands behaves corretly? 

  • Hi Tomer,

    Could you please provide a register dump of the 954 that is not working as expected?

    Thanks,
    Zoe